Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device
Reexamination Certificate
2002-02-04
2003-09-09
Nguyen, Tuan H. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
C257S197000, C257S200000
Reexamination Certificate
active
06617619
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally in the field of fabrication of semiconductor devices. More particularly, the present invention is in the field of fabrication of heterojunction bipolar transistors.
2. Related Art
In a silicon-germanium (“SiGe”) heterojunction bipolar transistor (“HBT”), a thin silicon-germanium layer is grown as the base of a bipolar transistor on a silicon wafer. The SiGe HBT has significant advantages in speed, frequency response, and gain when compared to a conventional silicon bipolar transistor. Cutoff frequencies in excess of 100 GHz, which are comparable to the more expensive gallium-arsenide based devices, have been achieved for the SiGe HBT.
The higher gain, speed and frequency response of the SiGe HBT are possible due to certain advantages of silicon-germanium, such as a narrower band gap and reduced resistivity. These advantages make silicon-germanium devices more competitive than silicon-only devices in areas of technology where high speed and high frequency response are required.
The advantages of high speed and high frequency response discussed above require, among other things, that parasitic capacitance in the SiGe HBT is minimized. One source of parasitic capacitance associated with the SiGe HBT is emitter to base capacitance. The practical effect of a capacitor is that it stores electrical charges that are later discharged, and the extra time required to charge and discharge the excess capacitance slows down the transistor. Because the benefits of high speed and high frequency response, as well as high gain, can be compromised by such excess capacitance, it is a goal of SiGe HBT design to reduce such excess capacitance to a minimum. For instance, by keeping the emitter to base capacitance low, improved SiGe HBT performance is achieved.
Parasitic emitter to base capacitance in a conventional SiGe HBT is composed of intrinsic and extrinsic components. The intrinsic component of the parasitic emitter to base capacitance is the emitter-base junction capacitance inherent in the SiGe HBT and is determined by various fabrication parameters in the SiGe HBT device. Therefore, the emitter-base junction capacitance can only be reduced by altering the fabrication parameters and performance of the device itself. For example, reduction in emitter-base junction capacitance could be achieved by making the active region width of the SiGe HBT smaller, but such a modification to the device architecture would alter the performance properties of the device.
The extrinsic component of the parasitic emitter to base capacitance in a conventional SiGe HBT results from portions of the polycrystalline silicon emitter that extend beyond the active area of the SiGe HBT. The portions of the conventional polycrystalline silicon emitter that extend beyond the active area are situated above the extrinsic base region of the conventional SiGe HBT, and thus create parasitic emitter to extrinsic base capacitance.
Various methods aimed at reducing the parasitic emitter to base capacitance are known in the art, but these methods have not produced the level of reduction desired or, in other instances, are impractical to implement. For example, one method proposed involves reducing the geometries of the SiGe HBT, particularly reducing the portions of the emitter that extend beyond the width of the active region and overlap extrinsic base regions. Unfortunately, such undesired overlapping can only be reduced to the extent permitted by current photolithography processes utilized to fabricate the emitter. Thus, a certain amount of overlapping is unavoidable because of the limitation in resolution with current photolithography technology. Another proposed method is directed to reducing the area of the active region of the SiGe HBT. Utilizing such a method would reduce the intrinsic component of the parasitic emitter-base junction capacitance, but as discussed briefly above, altering the device geometry would require altering the device fabrication process and can compromise the device's performance and reduce its effectiveness.
Thus, there is a need in the art for an emitter in a SiGe HBT that achieves a reduction in parasitic emitter to base capacitance without diminishing the performance of the SiGe HBT.
SUMMARY OF THE INVENTION
The present invention is directed to structure and method for a selective epitaxial HBT emitter. The present invention addresses and resolves the need in the art for an emitter in a SiGe HBT that achieves a reduction in parasitic emitter to base capacitance without diminishing the performance of the SiGe HBT.
According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor, for example, may be an NPN silicon-germanium-carbon heterojunction bipolar transistor. The heterojunction bipolar transistor further comprises an epitaxial emitter selectively situated on the top surface of the base. For example, the epitaxial emitter may be N-type single-crystal silicon. The heterojunction bipolar transistor further comprises an etch stop layer situated on the top surface of the base, where the etch stop layer is in contact with the epitaxial emitter. The etch stop layer, for example, may be silicon dioxide.
According to this exemplary embodiment, the heterojunction bipolar transistor further comprises a first spacer and a second spacer situated on the etch stop layer, where the epitaxial emitter is situated between the first spacer and the second spacer. The first spacer and the second spacer, for example, may be LPCVD silicon nitride. The heterojunction bipolar transistor further comprises a dielectric layer deposited on the first and second spacers. For example, the dielectric layer may be silicon nitride. The heterojunction bipolar transistor further comprises an antireflective coating layer deposited over the dielectric layer. The antireflective coating layer, for example, may be silicon oxynitride. In another embodiment, the present invention is a method that achieves the above-described heterojunction bipolar transistor. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.
REFERENCES:
patent: 6251738 (2001-06-01), Huang
patent: 6316818 (2001-11-01), Marty et al.
patent: 6337494 (2002-01-01), Ryum et al.
patent: 6384469 (2002-05-01), Chantre
Racanelli Marco
Schuegraf Klaus F.
U'Ren Greg D.
Farjami & Farjami LLP
Newport Fab LLC
Nguyen Tuan H.
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