Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-10-11
2004-08-17
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185050, C257S315000
Reexamination Certificate
active
06778438
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure, fabrication method, and operating method for a NOR-type flash memory, and particularly to the structure, fabrication method and operating method for a NOR-type flash memory using a channel erase scheme to perform an erase function.
2. Description of the Related Art
INTEL corporation provides an ETOX-type flash memory, in which, to erase data, high voltage is applied to its source and the gate is simultaneously grounded. The following disadvantages occur. When performing the erase, the high voltage applied to the source generates band-to-band tunneling conduction, resulting in large current flowing from the source to the substrate. Further, the high voltage on the source also generates hot holes that are easily trapped in the tunneling oxide layer, resulting in so-called gate disturbance, thus lowering the capability of memory cell for holding charges. Moreover, the hot holes injected into the tunneling oxide layer also degrade the tunneling oxide layer, and lower its endurance. As well, in order to provide a high voltage on the source, a double diffused graded junction structure has to be designed, but the structure occupies quite a large area of the substrate, thus increasing the difficulty of maintaining reduced size in memory devices.
AMD Inc. provides another flash memory in U.S. Pat. No. 5,077,691, in which a high negative voltage is applied to the gate and a relatively lower positive voltage to the source of the memory cell. Although this design may resolve the aforementioned problems, the erasing function is still performed via the source, i.e. the so-called source-terminal erase. Since the erase characteristics for the device utilizing the scheme of source-terminal erase are usually nonuniformity, this device generally has very low reliability. Additionally, circuit designers must also take the negative voltage circuit design into account, so that this device requires circuit design of high complexity, with more varieties of peripheral circuit elements.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a NOR-type flash memory structure using a channel erase scheme to erase data. The present structure has high reliability in preventing nonuniform erase situations, and the high voltages used are all positive, thereby decreasing the complexity of circuit design.
Further, it is another object of the present invention to provide a fabrication method for NOR-type flash memory.
In addition, it is another object of the present invention to provide an operating method for NOR-type flash memory.
The present invention provides a flash memory structure, briefly described as follows. A device isolation region is located in a substrate to define an active area. A deep well of first conductive type is located in the substrate, wherein the deep well of first conductive type is disposed in the active area and the area below the device isolation region. A stacked gate structure is located on the substrate, and is composed of a floating gate, a dielectric layer, and a control gate. A tunneling oxide layer is located between the stacked gate structure and the substrate. A well of second conductive type is located in the area corresponding to the drain between the adjacent stacked gate structures, and is disposed in the area below the device isolation region located between the adjacent stacked gate structures. A spacer is located on both sides of the stacked gate structure. A source and a drain are in the active area located on both sides of the control gate, wherein the drain is enclosed by the well of second conductive type, and the source is electrically connected via the deep well of first conductive type.
According to an embodiment of the present invention, in the aforementioned flash memory structure, the deep well of first conductive type is an n-well region, and the well of second conductive type is a p-well region, and the source and the drain are n-doped regions.
The present invention also provides a fabrication method for flash memory, briefly described as follows. A device isolation is formed in a substrate to define a striped active area. A deep well of first conductive type is formed in the substrate, and the deep well of first conductive type is disposed in the active area and the area below the device isolation region. Thereafter, a tunneling oxide and an electrically conductive layer are formed on the active area, and then on the top of these two layers, a dielectric layer and a second electrically conductive layer are formed. Thereafter, the second electrically conductive layer, the dielectric layer and the first electrically conductive layer are defined to convert the second and first electrically conductive layers into the control gate and floating gate of a stacked gate structure. Subsequently, a well of second conductive type is formed in the area corresponding to the drain between the adjacent stacked gate structures, and is disposed in the area below the device isolation region located between the adjacent stacked gate structures. Thereafter, a drain is formed on the active area located on one side of the stacked gate structure, wherein the drain is enclosed by the well of second conductive type. Then, a spacer is formed on both sides of the stacked gate structure, and a source is formed in the active area located on the other side of the control gate, wherein the source is located on both sides of the well of second conducive type, and electrically connected via the deep well of first conductive type.
The present invention further provides an operating method to erase, programming and reading data on a flash memory, wherein a wordline voltage, a bitline voltage and a p-well voltage are respectively applied to the control gate, drain and p-well, each of which corresponds to a selected flash memory cell, the source of the flash memory is a common source mutually connected via a deep n-well, the drain is commonly used by two adjacent flash memory cells, and the p-well is located in the area corresponding to the drain between two adjacent control gates. The operating method of the present invention to erase, programming and reading data is described as follows. A high voltage is applied to a p-well, maintaining the wordline in a ground state, and the bitline and the common source are in a floating state to perform an erase operation. After a high voltage is applied to the wordline, a voltage lower than that applied to the wordline is applied to the bitline, maintaining the common source voltage, and the p-well voltage at the ground state to perform a programming operation. With proper voltage applied to the wordline, a voltage lower than that applied to the wordline is applied to the bitline to carry out a read operation.
According to an embodiment of the present invention, the p-well voltage is about 20V, when an erase operation is performed. When a programming operation is performed, the wordline voltage is between 10V and 20V, and the bitline voltage is between 5V and 6.5V. When a read operation is performed, the bitline voltage is 1.5V.
REFERENCES:
patent: 5077691 (1991-12-01), Haddad et al.
patent: 6169693 (2001-01-01), Chan et al.
patent: 6240021 (2001-05-01), Mori
patent: 6501685 (2002-12-01), Hsu et al.
Hung Chih-Wei
Sung Da
Ladas & Parry
Nguyen Tan T.
Powerchip Semiconductor Corp.
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