Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-08-08
2002-05-21
Paladini, Albert W. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S266000, C257S698000
Reexamination Certificate
active
06392158
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention involves a structure formed on a substrate and equipped with an electrical contact or several electrical contacts as well as a process for obtaining such a structure.
The invention applies in particular to any type of structure (for example. an acceleration meter, a pressure sensor or an actuator) formed on the surface of an appropriate layer.
This layer can be electrically conducting (in silicon or polysilicon for example) and formed on an electrical insulator.
2. Discussion of the Background
Electromechanical micro-systems formed on chips are already known from surface manufacturing techniques.
In order to electrically connect a chip on which such a micro-system is formed with the outside world, metallic contact studs are formed on the surface of this chip to act as an interface between the electrically active zones of the chip and the outside world, this latter being for example an electronic measuring device.
In some cases, the micro-system must be maintained in a confined medium for hermetic reasons.
In such cases, it is known that the chip can be equipped with a cap which encloses the micro-system.
This is schematically illustrated in FIG.
1
.
The figure shows the chip
2
and the contact studs
4
which are connected by contact lines
6
to the electrically active zones (not shown) of the chip.
It also shows the cap
8
which covers the micro-system (not shown) but not the contact studs which are usually accessible on one side of the chip.
Such a cap complicates the formation of electrical contacts with the micro-system.
The formation of the contact lines
6
which end at the contact studs
4
, with an electrical passage from the zone covered by the cap
8
to its exterior and more precisely to the zone where the contact studs appear, affects the evenness of the zone which is to be sealed.
To form each contact line
6
, a several hundred nanometers thick metallic deposit is formed.
Such deposits create steps which can be obstacles for sealing, especially if the sealing is to be hermetic.
This is schematically illustrated by
FIG. 2
which is a schematic cross-section view of
FIG. 1
at the level of the contact lines
6
.
FIG. 2
also shows electrically insulating layers
10
which are interposed between the contact lines
6
and the chip
2
itself.
As an example, Silicon Direct Binding requires perfect evenness of the chip and the cap.
The steps are thus a crippling hindrance for this type of sealing.
Anodic sealing, on the other hand, does not require perfect evenness. This does not guarantee a hermetic seal however.
This is schematically illustrated in FIG.
3
.
FIG. 3
shows that a glass substrate
12
and a silicon chip
2
can be sealed to each other on both sides of the steps but that there are areas
14
which are poorly sealed which act as vents.
This means that the anodic seal is not hermetic.
Another known technique involves metallisation through a hole on a glass cap which is anodically sealed so that no contact line crosses the seal.
The following document may be consulted on this subject:
M. Esashi, Y. Matsumoto and S. Shoji, “Absolute Pressure Sensors by Air-tight Electrical Feedthrough Structure”, Sensors and Actuators, A21-A23 (1990) 1048-1052.
This is schematically illustrated by
FIG. 4
which shows the chip
2
which is sealed to the glass cap
16
.
This glass cap is crossed by a hole
17
and
FIG. 4
shows the metallic layer
18
resulting from the metallisation of the chip through this hole.
It also shows metallic layers
19
which were formed on the cap at the time of the formation of the layer
18
.
The active structure (an acceleration meter, pressure sensor or actuator) and the glass cap are each formed separately before being sealed to each other.
This known technique could possibly be applied to sealing a chip and a silicon cap.
This raises the issue of compatibility of treatment between the forming of the hole, the type of sealing, the preparation of the surface before metallization and the annealing of this metallization.
The main drawback of this known technique is that the various substrates are first treated and then assembled.
In addition, this technique requires the use of a glass cap and a rather complex process for making this cap.
SUMMARY OF THE INVENTION
This invention aims to overcome the previous drawbacks.
The invention provides a structure (e.g. the micro-system) and electrical contacts to the structure in a stack of layers, this stack formed before the making of the structure.
This stack could be a usual monolithic stack or a standard stack of the SIMOX type for example.
The structure equipped with electrical contacts is obtained with this stack.
The capping of this structure, if required, can be obtained by various techniques such as:
sealing with a polymer
anodic sealing or
sealing with a technique called “Silicon Direct Bonding”.
According to the invention, each electrical contact is formed on the rear side of the layer in which the structure is formed, through a hole formed in the substrate on which this layer lies.
This approach differs from the state of the art mentioned above in which electrical contacts are only formed on the front side of the layer.
More precisely, the invention resolves the following problems: (a) obtaining a structure which includes a layer formed on a substrate and equipped with an electrical contact formed facing this substrate and electrically insulated from it (thus minimizing the stray capacitance which exists between the contact and the substrate) and (b) being able to form the contact during the very last phase of manufacturing of the structure and, more precisely, determining an architecture which demarcates the contact(s) so that the contact(s) can be made with a simple conducting deposit without an additional etching step.
The invention defines a stack including a micro-system having an electrical contact to connect the micro-system to the outside world, a substrate having a first layer formed on the substrate, a through hole extending in an axial direction of the substrate and configured to reveal a rear side of the first layer and to provide a passage to electrically connect to the electrical contact, and a cavity located at an end of the through hole close to the first layer, wherein the cavity has dimensions transverse to the axial direction larger than a diameter of the through hole and forms an overhanging edge around the through hole.
According to a particular embodiment of the invention structure, the first layer is electrically conducting, the substrate includes a second layer which is electrically insulating and the first layer rests on this second layer.
This invention also involves a process for manufacturing a structure equipped with at least one electrical contact, this process being characterised in that a first layer is formed on a substrate, the structure is formed in this first layer, on its front side, and at least one hole through the substrate, this hole exposing the rear side of the first layer, and with the electrical contact formed on this rear side, facing the hole, in a cavity overhung by the edge of the hole closest to the first layer, this overhang allowing for electrical insulation of the contact of the substrate.
According to a preferred embodiment of the invention process, a sacrificial layer is formed on the substrate, then the first layer on this sacrificial layer, this sacrificial layer is etched through the hole so that the edge of the hole closest to the first layer forms an overhang with respect to it and the electrical contact is formed on the rear side of the first layer through the hole.
The electrical contact is preferably formed by depositing of metal on the rear side of the first layer through the hole.
According to a particular embodiment of the invention process, the first layer is electrically conducting, the substrate includes a second layer which is electrically insulating and the sacrificial layer is formed on this second layer, then the first layer on this sacrificial
Caplet Stephane
Delaye Marie-Therese
Alcala José H.
Commissariat a l'Energie Atomique
Paladini Albert W.
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