Structure design for minimizing on-chip interconnect inductance

Details Structure design for minimizing on-chip interconnect inductance Structure design for minimizing on-chip interconnect inductance

2011-05-31

2011-05-31

Lee, Benny (Department: 2817)

Wave transmission lines and networks

Long lines

Strip type

C333S246000

Reexamination Certificate

active

07952453

ABSTRACT:
A semiconductor device comprising a signal line and ground line is disclosed. The signal line comprises an opening and at least a portion of the ground line is in the opening in the signal line.

REFERENCES:
patent: 4233579 (1980-11-01), Carlson et al.
patent: 6144268 (2000-11-01), Matsui et al.
patent: 6985055 (2006-01-01), Minami
patent: 7088204 (2006-08-01), Kanno
patent: 2004357011 (2004-12-01), None
CN Office Action mailed Jun. 26, 2009, cited in parent.
English Abstract of JP2004357011, pub. Dec. 16, 2004.
English language, machine translation (generated by Japan Patent Office Web site) of published application JP2004-357011, published Dec. 16, 2004.

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