Structure and process of via chain for misalignment test

Details Structure and process of via chain for misalignment test Structure and process of via chain for misalignment test

2000-11-10

2002-10-01

Fourson, George (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

C438S627000

Reexamination Certificate

active

06459151

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a structure or a process of via chain, especially for testing the misalignment in the semiconductor process.
BACKGROUND OF THE INVENTION
In the semiconductor process, the via chain is a common structure for testing. Generally, for being easy to test, the process of the integrated circuit will add some test keys on the edge region of the integrated circuit. Owing to the fact that the test keys are almost connected to the register devices used for testing, the signal lines are generally connected to each other in series or parallel connections. Therefore, it forms a regular via chain.
FIG. 1
is the structure of via chain according to the prior art. The via chain is formed by the upper metal line
13
, the via
12
, and the lower metal line
11
. The diameters of the metal lines
11
and
13
are bigger than that of the via
12
, so there is no alignment problem exists. Thus, a certain level misalignment is acceptable in the processing. However, through the process advancement, the diameter of metal line is smaller and smaller. Therefore, the structure that the diameter of the via chain is bigger than that of the via cannot meet the demand of the current technology of semiconductor manufacturing.
FIGS. 2A and 2B
are also the structure of via chain according to the prior art. As shown in
FIG. 2
, the diameters of the upper metal line
21
and the lower metal line
11
are changed to be very small. However, the diameter of the via
12
cannot be reduced under the current process technology. Thus, the width of the dielectric layer is the same as that of the metal line, sometime even bigger.
FIG. 2A
is a top view. The left side view is the accurate condition of alignment of the upper metal line
21
and the via
12
. Upon accurate alignment, basically, the upper metal line
21
will completely cover the left and right vias
12
. However, due to the fact that the traditional structure of via chain is arranged in a single direction, the upper metal line
21
will shift for a distance
22
when there is a misalignment (see the right side view of FIG.
2
A). The misalignment causes the right via
12
to be incompletely covered by the upper metal line
21
. The slight shifted distance definitely affects the reliability and the yield of the process. However, as
FIG. 2B
showing the structural cross-section of via chain, the misalignment cannot be accurately detected because the via chain is still in the connecting condition even if there is a slight shifted distance
22
(see the right side view of FIG.
2
B).
Thus, after the development of the traditional semiconductor process, it causes the troubling situation that the misalignment of via chain cannot be accurately determined. Therefore, it will cause the significant defects in reliability and yield in the process.
It is therefore tried by the applicant to deal with the above situation encountered in the prior art.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to propose a structure of the via chain to accurately detect the misalignment for assuring the reliability and yield.
It is therefore another object of the present invention to propose a process of producing the via chain for accurately detecting the misalignment.
According to the present invention, a structure of a via chain for misalignment test comprises a substrate, a first via chain formed on the substrate in a first direction, and a second via chain formed on the substrate in a second direction, thereby enabling the misalignment test.
Certainly, the substrate can be a semiconductor substrate. The first via chain comprises a first metal section, two vias, and a second metal section, and the first metal section and second metal section are in a first direction. The first metal section and second metal section is formed of a first chain structure by connecting with said vias. The second via chain comprises a third metal section, two vias, and a fourth metal section, and the third metal section and fourth metal section are in a second direction. The third metal section and fourth metal section is formed of a second chain structure by connecting with said vias.
Preferably, the first via chain is perpendicular to said second via chain.
According to another aspect of the present invention, a process of forming a via chain for misalignment test comprises providing a substrate, forming a first via chain on the substrate in a first direction, and forming a second via chain on the substrate in a second direction.
According to additional aspect of the present invention, a process of forming a via chain for misalignment test comprises providing a substrate, and forming a first via chain on the substrate in a first direction and a second via chain on the substrate in a second direction simultaneously.


REFERENCES:
patent: 4670091 (1987-06-01), Thaomas et al.
patent: 6320396 (2001-11-01), Nikawa
patent: 2001/0001427 (2001-05-01), Atakov et al.
patent: 2001/0015464 (2001-08-01), Tamaki
“Intertwined Integrated Circuit Testing Chain” IBM Technical Disclosure Bulletin, Feb. 1986, US, vol. 28, pp. 3959-3960.*
“Test Structure for Semiconductor Chips”, IBM Technical Disclosure Bulletin, Aug., 1976, vol. 19, pp. 898-899.

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