Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
2006-12-07
2008-12-23
Parekh, Nitin (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S773000, C257S786000, C257SE21599
Reexamination Certificate
active
07468544
ABSTRACT:
A wafer level package comprises a wafer having a plurality of dice formed thereon; a thinner metal cover with a cavity formed therein attached on the wafer by an adhesive material to improve thermal conductivity of the package. A protection film is formed on back side of the metal cover and filled into the cavity, thereby facilitating for laser marking and obtaining a better sawing quality of the package.
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patent: 6184573 (2001-02-01), Pu
patent: 6607941 (2003-08-01), Prabhu et al.
patent: 7101735 (2006-09-01), Noma et al.
patent: 7256073 (2007-08-01), Noma et al.
patent: 2004/0232517 (2004-11-01), Furuhata
Advanced Chip Engineering Technology Inc.
Kusner & Jaffe
Parekh Nitin
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