Structure and process for optimizing the characteristics of I.su

Details Structure and process for optimizing the characteristics of I.su Structure and process for optimizing the characteristics of I.su

1979-08-27

1982-04-20

Larkins, William D.

357 89, 357 91, 357 92, H01L 2704, H03K 19081

Patent

active

043262120

ABSTRACT:
An improved I.sup.2 L structure and process are disclosed which reduces the minority carrier charge storage, increases the emitter injection efficiency and reduces the emitter diffusion capacitance in the upward injecting vertical NPN transistor and reduces the minority carrier charge storage and increases the collector efficiency in the lateral PNP transistor. This is accomplished by ion-implanting a p-type region in the epitaxial layer, through an insulating layer on the surface having an emitter window over the vertical NPN transistor, so that its concentration contour peak follows the contour of the insulating layer so as to be closer to the subemitter in the intrinsic base region than in the extrinsic base region of the vertical transistor, thereby imposing a concentration gradient induced electric field in the intrinsic base region which will aid in the movement of the minority carrier charges from the buried emitter into the intrinsic base region of the vertical transistor while at the same time reducing the tendency of the minority carriers to stay in the region of the epitaxial layer between the subemitter and the base in the vertical NPN and between the buried N region and the collector region of the lateral PNP.

REFERENCES:
patent: 3704399 (1972-11-01), Glaise
patent: 3878551 (1975-04-01), Callahan, Jr.
patent: 3945857 (1976-03-01), Schinella et al.
patent: 3993513 (1976-11-01), O'Brien
patent: 4058419 (1977-11-01), Tokumaru et al.
patent: 4064526 (1977-12-01), Tokumaru et al.
Mulder et al, IEEE J. of Solid State Circuits, vol. SC 11, No. 3, Jun. 1976, pp. 379-385.
Hennig et al, IEEE J. of Solid-State Circuits, vol. SC 12, No. 2, Apr. 1977, pp. 101-109.

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