Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With provision for cooling the housing or its contents
Reexamination Certificate
2007-08-28
2011-10-11
Tran, Minh-Loan T (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With provision for cooling the housing or its contents
C257S714000, C257S777000, C257SE23097
Reexamination Certificate
active
08035223
ABSTRACT:
A structure and method for thermal management of integrated circuits. The structure for thermal management of integrated circuits includes first and second substrates bonded together, at least one of the first and second substrates including at least one circuit element, an entrance through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, an exit through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, a bonding element forming a seal between the first and second substrates and forming a space between the first and second substrate, and a coolant channel formed in the space between the first and second substrates such that a fluid entering the entrance through-hole transits the coolant channel and the exit through-hole to provide cooling to the circuit element. The method supplies a fluid through the entrance through-hole, flows the fluid through the coolant channel between the first substrate and second substrates, and removes the fluid from the coolant channel through the exit through-hole.
REFERENCES:
patent: 5001548 (1991-03-01), Iversen
patent: 5225707 (1993-07-01), Komaru et al.
patent: 5378926 (1995-01-01), Chi et al.
patent: 6242778 (2001-06-01), Marmillion et al.
patent: 6391673 (2002-05-01), Ha et al.
patent: 6992382 (2006-01-01), Chrysler et al.
patent: 2005/0269665 (2005-12-01), Wylie et al.
patent: 2007/0063337 (2007-03-01), Schubert et al.
patent: 2007/0085198 (2007-04-01), Shi et al.
patent: 2007/0126103 (2007-06-01), Shi
Jeffrey A. Davis et al, “Interconnect Limits on Gigascale Integration (GSI) in the 21stCentury”, Proceedings of the IEEE, vol. 89, No. 3, Mar. 2001, pp. 305-324.
Kaustav Banerjee, et al., “3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-On-Chip Integration”, Proceedings of the IEEE, Vo. 89, No. 5, May 2001, pp. 602-633.
Armin Klumpp, et al. “Chip-To-Wafer Stacking Technology for 3D System Integration”, 2003 Electronic Components and Technology Conference, pp. 1080-1083.
Jae-Mo Koo, et al., “Integrated Microchannel Cooling for Three-Dimensional Electronic Circuit Architectures”, Journal of Heat Transfer, Jan. 2005, vol. 127, pp. 49-58.
Yoshihiro Tomita, et al. “Copper Bump Bonding With Electroless Metal Cap on 3 Dimensional Stacked Struture”, 2000 Electronics Packaging Technology Conference, pp. 286-291.
Yoshihiro Tomita, et al., “Cu Bump Interconnections in 20μm Pitch Utilizing Electroless Tin-Cap on 3D Stacked LSI”, 2001 Int'l Symposium on Electronic Materials and Packaging, pp. 107-114.
Bower Christopher A.
Garrou Philip
Williams Charles Kenneth
Cruz Leslie Pilar
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
Research Triangle Institute
Tran Minh-Loan T
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