Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2002-12-27
2004-08-10
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S777000, C257S797000, C257S723000, C257S724000, C257S784000, C438S686000, C438S107000, C438S109000, C438S108000, C438S118000, C438S455000, C438S458000
Reexamination Certificate
active
06774477
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure and method of stacking multiple semiconductor substrates of a composite semiconductor device, and more particularly, to a structure and method of stacking multiple semiconductor substrates of a composite semiconductor device which can align the semiconductor substrates when stacking and bonding the semiconductor substrates after fabricating two or more semiconductor devices of the composite semiconductor device on a semiconductor substrate.
2. Description of the Related Art
Recently, semiconductor devices used for a composite semiconductor device such as MML (Merged Memory and Logic), SOC (System on Chip) or the like in the field of system integrated circuits have made a rapid progress. Generally, the semiconductor device has a memory device, such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), Flash EEPROM, EPROM or the like, and a logic device, which is formed on a semiconductor substrate.
In a fabrication method of such a composite semiconductor device, if the size of a memory increases, the overall size of the semiconductor device also increases since the memory device and the logic device area formed on the same semiconductor substrate. Therefore, there is a problem in developing various products such as a video controller mounted with a high capacity memory, a SRAM, a MCU (Micro Controller Unit) mounted with a flash memory. Also, it is difficult to optimize the logic device requiring a high speed because the composite semiconductor device is fabricated based a memory process.
Hence, the composite semiconductor device with a memory device and logic device is implemented as a single device by separately forming the memory device and the logic device on different semiconductor substrates and then stacking and joining these semiconductor substrates to form multiple substrates.
FIG. 1
is a process chart showing a method of stacking multiple semiconductor substrates of a composite semiconductor device according to the prior art. Referring to
FIG. 1
, a method for fabricating a memory device and a logic device on multiple semiconductor substrates according to the prior art will now be explained.
As shown in
FIG. 1
, a first interlayer insulating layer
11
is formed on a first semiconductor substrate
10
in which a memory device (not shown) is provided. Gate electrodes, source/drain electrodes of a memory cell transistor serving as a memory device is formed on the first semiconductor substrate
10
. Multiple poly-silicon layers and multiple metal wires forming bit lines, capacitors and the like of the memory cell transistor are formed on the first interlayer insulating layer
11
. Contact holes for electrically connecting source/drain regions of the memory cell transistor and via holes for connecting a metal wire to another metal wire are formed. Next, first via holes
12
vertically connected with a final metal wire of the memory cell transistor are formed on the first interlayer insulating layer
11
and first bonding pads
13
connected with the first via holes
12
are formed on the first interlayer insulating layer
11
. A first protection layer
14
is formed on the structure with the first bonding pads
13
and then the first bonding pads
13
are exposed by selectively etching back the first protection layer
14
.
Subsequently, a second interlayer insulating layer
21
is formed on a second semiconductor substrate
20
in which a logic device (not shown) is provided. Gate electrodes, source/drain electrodes of the logic transistor serving as a logic device are formed on the second semiconductor substrate
20
. Multiple metal wires of the logic transistor are formed on the second inter-insulating layer
21
. Contact holes for electrically connecting source/drain regions of the logic transistor and via holes for connecting a metal wire to another metal wire are formed. Next, second via holes
22
vertically connected with a final metal wire of the logic transistor are formed on the second interlayer insulating layer
21
and second bonding pads
23
connected with the second via holes
22
are formed on the second interlayer insulating layer
21
. A second protection layer
24
is formed on the structure with the second bonding pads
23
and then the second bonding pads
23
are exposed by selectively etching back the second protection layer
24
.
As shown in
FIG. 1
, in order to connect each memory device and logic device formed on the first semiconductor substrate
10
and the second semiconductor substrate
20
, respectively, the second semiconductor is turned upside down so as to join the first bonding pads
13
of the first semiconductor substrate
10
to the second bonding pads
23
of the second semiconductor substrate
20
and the first and second semiconductors
10
and
20
are stacked. When the stacked first and second semiconductor substrates
10
and
20
are annealed at a temperature of 300° C. to 450° C., the first bonding pads
13
of the first semiconductor
10
and the second bonding pads
23
of the second semiconductor
20
are electrically connected.
Since a conventional stacking technique for multiple semiconductor substrates of a composite semiconductor device, as mentioned above, does not use a mask alignment key for joining the first and second semiconductor substrates
10
and
20
, a misalignment of the first bonding pads
13
and the second bonding pads
23
is caused, making it difficult to electrically connect the first bonding pads
13
and the second bonding pads
23
.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure for stacking multiple semiconductor substrates of a composite semiconductor device which can align the semiconductor substrates using align marks when joining bonding pads of semiconductor substrates and stacking them by providing the alignment marks as well as the bonding pads on the upper surface of the semiconductor substrates having two or more semiconductor devices of a composite semiconductor device formed thereon.
It is another object of the present invention to provide a method of stacking multiple semiconductor substrates of a composite semiconductor device which can accurately align the multiple semiconductor substrates by joining bonding pads of the semiconductor substrates and stacking them after fabricating two or more semiconductor devices of the composite semiconductor device on the semiconductor substrates, forming alignment marks as well as the bonding pads on the upper surface of each semiconductor substrate and then aligning the semiconductor substrates using these alignment marks.
In accordance with an aspect of the present invention, there is provided a structure for stacking multiple semiconductor substrates of a composite semiconductor device, wherein the composite semiconductor device has at least two semiconductor devices, the structure comprising: a first semiconductor substrate having a first interlayer insulating layer for a first semiconductor device, first via holes formed in the first interlayer insulating layer for connecting the first semiconductor device, first bonding pads formed on the upper surface of the first interlayer insulating layer and connected with the first via holes and first alignment marks arranged on the outer periphery of the substrate; and a second semiconductor substrate having a second interlayer insulating layer for a second semiconductor device, second via holes formed on the second interlayer insulating layer for connecting the second semiconductor device, second bonding pads formed on the upper surface of the second interlayer insulating layer and connected with the second via holes and second alignment marks arranged on the outer periphery of the substrate; and wherein the first bonding pads of the first semiconductor substrate and the second bonding pads of the second semiconductor substrate are joined by aligning the first alignment marks of the first semiconductor substrate and the se
Erdem Fazli
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
Tran Minhloan
LandOfFree
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