Structure and method of manufacture for MOS field effect transis

Details Structure and method of manufacture for MOS field effect transis Structure and method of manufacture for MOS field effect transis

1992-11-17

1994-04-26

Quach, T. N.

Fishing, trapping, and vermin destroying

437 35, 437 41, 437978, H01L 21336

Patent

active

053066553

ABSTRACT:
Structures and methods of manufacture are described for a MOS FET that is suitable for extreme miniaturization, of a type in which lightly doped drain and source diffusion regions are formed respectively adjoining the conventional highly doped drain and source diffusion regions in the semiconductor substrate surface, for reducing electric field concentration in the drain region. The underside of the gate electrode of the FET is formed with a downwardly protruding convex shape, so that a thick region of gate insulation film is positioned between the drain diffusion regions and the most closely adjacent part of the gate electrode, whereby gate-to-drain stray capacitance and the vertical component of electric field within the lightly doped drain diffusion region are reduced. The underside of the gate electrode can be formed in the required shape by various methods which effectively utilize self alignment and are easily adapted to currently used types of LSI manufacturing process.

REFERENCES:
patent: 4885259 (1989-12-01), Osinski et al.
patent: 5015598 (1991-05-01), Verhaar
patent: 5061647 (1991-10-01), Roth et al.
patent: 5217913 (1993-06-01), Watabe et al.
"A Novel Submicron LDD Transistor With Inverse T-Gate Structure", Huang et al., IEDM 1986, pp. 742-745.
"Design and Characteristic of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor" Ogura et al., Transactions on Electron Devices, vol. ED-27, No. 8, Aug. 1980, pp. 1359-1367.

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