Structure and method of making strained semiconductor CMOS...

Details Structure and method of making strained semiconductor CMOS... Structure and method of making strained semiconductor CMOS...

2005-05-10

2005-05-10

Nguyen, Thanh (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

C257S066000, C257S067000, C257S069000

Reexamination Certificate

active

06891192

ABSTRACT:
A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

REFERENCES:
patent: 6703648 (2004-03-01), Xiang et al.
patent: 20040065927 (2004-04-01), Bhattacharyya

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