Structure and method of implementing power savings during...

Details Structure and method of implementing power savings during... Structure and method of implementing power savings during...

2007-03-21

2009-02-17

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030

Reexamination Certificate

active

07492662

ABSTRACT:
A random access memory device includes an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Address decoder logic in signal communication with the array is configured to receive a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated.

REFERENCES:
patent: 5546353 (1996-08-01), Phillips et al.
patent: 6295595 (2001-09-01), Wildenberg et al.
patent: 2006/0047493 (2006-03-01), Gooding
patent: 2007/0247897 (2007-10-01), Katti

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