Structure and method for virtual-to-physical address translation

Details Structure and method for virtual-to-physical address translation Structure and method for virtual-to-physical address translation

1994-01-28

1997-02-25

Moore, David K.

395406, 395413, G06F 1200

Patent

active

056066830

ABSTRACT:
A structure and a method are provided in a table lookaside buffer (TLB) for translating a virtual memory address to a physical memory address. The virtual memory address is computed by adding to a base address an offset value. In the TLB of the present invention, each entry of the TLB is stored a previous base address, a partial sum of the previous virtual memory address computation, the sign bit of the previous offset value, and the value of the carry bit at the position of the sign bit of the previous offset value in the previous virtual memory address computation. The present invention is especially applicable to a data TLB used in conjunction with a two-way set associative data cache memory.

REFERENCES:
patent: 4251860 (1981-02-01), Mitchell et al.
patent: 5150471 (1992-09-01), Tipon et al.
patent: 5263140 (1993-11-01), Riordan
patent: 5381537 (1995-01-01), Baum et al.
patent: 5420992 (1995-05-01), Killian et al.
Excerpt from Section 16.6 "Computation Structures" by Stephen A. Ward and Robert H. Halstead, MIT Press (1990), pp. 480-490.

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