Structure and method for suppressing sub-threshold leakage...

Details Structure and method for suppressing sub-threshold leakage... Structure and method for suppressing sub-threshold leakage...

2007-05-01

2007-05-01

Lam, David (Department: 2827)

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C365S154000, C365S189110

Reexamination Certificate

active

10701835

ABSTRACT:
Techniques for reducing leakage power in the transistors of integrated circuits are provided. Suppressing sub-threshold leakage techniques can be applied to memory cells that drive the gates of the transistors, memory cells that drive the sources of the transistors, and level shifters that drive the gates of the transistors. In these techniques, an appropriate gate to source voltage (VGS) can be applied to a transistor in its off state. Of importance, this VGScan under-drive the transistor, which significantly reduces the sub-threshold leakage of that transistor. These techniques fail to affect a transistor in its on state, thereby ensuring that high speed performance of the integrated circuit can be maintained.

REFERENCES:
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patent: 6166985 (2000-12-01), McDaniel et al.
patent: 6538954 (2003-03-01), Kunikiyo
patent: 6807109 (2004-10-01), Tomishima
patent: 6829194 (2004-12-01), Honda et al.
patent: 7042756 (2006-05-01), Madurawe
patent: 2005/0091630 (2005-04-01), Madurawe

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