Structure and method for shifting and reordering a plurality of

Details Structure and method for shifting and reordering a plurality of Structure and method for shifting and reordering a plurality of

1994-08-03

1995-12-19

Safourek, Benedict V.

Multiplex communications

Wide area network

Packet switching

36471508, G06F 700

Patent

active

054775434

ABSTRACT:
A shifter circuit and method for simultaneously and independently shifting and reordering a plurality of data bytes. The shifter circuit includes first and second registers which each receive a plurality of data bytes. The first register is coupled to a plurality of first buses, with each of the first buses receiving a data byte from the first register. Similarly, the second register is coupled to a plurality of second buses, with each of the second buses receiving a data byte from the second register. A multiplicity of third buses are coupled to the first and second buses. A byte shifting multiplexer is coupled to each of the third buses. A plurality of bit shifting multiplexer are coupled to the byte shifting multiplexers, with each bit shifting multiplexer being coupled to a pair of byte shifting multiplexers. A control circuit is coupled to the byte shifting and bit shifting multiplexers. The control circuit provides for independent control of each of the byte shifting multiplexers. The control circuit also provides for independent control of each of the bit shifting multiplexers.

REFERENCES:
patent: 4807172 (1989-02-01), Nukiyama
patent: 4931925 (1990-06-01), Utsumi et al.
patent: 4962511 (1990-10-01), Tokumaru
patent: 5166898 (1992-11-01), Ishihara

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