Excavating
Patent
1997-04-30
1999-04-27
Beausoliel, Jr., Robert W.
Excavating
324765, G01R 3112
Patent
active
058987061
ABSTRACT:
The present invention is directed to an apparatus and method for reliability testing of an integrated circuit. The present invention provides a test structure and method for testing gate and node dielectrics of an integrated circuit wherein a self-heating gate structure is integrated with the product structure itself. Selected conductive lines within the product structure are used as heater elements to provide temperature stressing of the integrated circuit. The localized self-heating gate structure is an integral part of the product chip. Thus, etch and deposition characteristics of the test structure are kept identical to the etch and deposition characteristics of the product itself. As low-voltage technologies make it harder to obtain significant acceleration due to voltage stressing, temperature stressing may be used instead to increase acceleration.
REFERENCES:
patent: Re32625 (1988-03-01), Schwarz et al.
patent: 3883802 (1975-05-01), Puri
patent: 3983479 (1976-09-01), Lee et al.
patent: 4730160 (1988-03-01), Cusack et al.
patent: 4739258 (1988-04-01), Schwarz
patent: 4739388 (1988-04-01), Packeiser et al.
patent: 5047711 (1991-09-01), Smith et al.
patent: 5049811 (1991-09-01), Dreyer et al.
patent: 5138427 (1992-08-01), Furuyama
patent: 5265057 (1993-11-01), Furuyama et al.
patent: 5276647 (1994-01-01), Matsui et al.
patent: 5297087 (1994-03-01), Porter
patent: 5298433 (1994-03-01), Furuyama
patent: 5317532 (1994-05-01), Ochii
patent: 5357193 (1994-10-01), Tanaka et al.
patent: 5392219 (1995-02-01), Birch et al.
patent: 5404099 (1995-04-01), Sahara
patent: 5406212 (1995-04-01), Hashinaga et al.
patent: 5451885 (1995-09-01), Birch et al.
patent: 5502399 (1996-03-01), Imai
patent: 5506450 (1996-04-01), Lee et al.
patent: 5532600 (1996-07-01), Hoshino
patent: 5590079 (1996-12-01), Lee et al.
patent: 5610866 (1997-03-01), McClure
patent: 5686843 (1997-11-01), Beilstein, Jr. et al.
"Self-Contained Chip Heater," IBM Technical Disclosure Bulletin, vol. 14, No. 6, p. 1770, Nov. 1971.
IBM Technical Disclosure Bulletin, vol. 14, No. 6 , Nov. 1971, Reilly et al, p. 1770.
Dufresne Roger Aime
Griffin Charles William
Hwang Chorng-Lii
Klaasen William Alan
Strong Alvin Wayne
Beausoliel, Jr. Robert W.
Chadurjian Mark F.
International Business Machines - Corporation
Iqbal Nadeem
LandOfFree
Structure and method for reliability stressing of dielectrics does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Structure and method for reliability stressing of dielectrics, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Structure and method for reliability stressing of dielectrics will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-690493