Structure and method for reducing parasitic leakage in a memory

Details Structure and method for reducing parasitic leakage in a memory Structure and method for reducing parasitic leakage in a memory

1995-03-24

1996-03-12

Thomas, Tom

Fishing, trapping, and vermin destroying

437 60, 437 61, 437 70, 437919, H01L 218242

Patent

active

054985641

ABSTRACT:
A semiconductor structure of merged isolation and node trench construction is presented, along with a method of fabrication, wherein an isolation implant layer is formed at the intersection of the storage node, isolation trench and field isolation region. The isolation implant layer has higher concentration of implant species than the adjacent field isolation region and is positioned to prevent a parasitic leakage mechanism between the source/drain diffusion of the storage node and an adjacent bit line contact diffusion. Implantation occurs during memory structure fabrication through the deep trench sidewall near the upper surface of the substrate.

REFERENCES:
patent: 4801988 (1989-01-01), Kenney
patent: 5041887 (1991-08-01), Kumagi et al.
patent: 5112762 (1992-05-01), Anderson et al.
patent: 5248894 (1993-09-01), Beasom

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