Structure and method for providing a reconfigurable emulation ci

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

364489, 364490, G06F 9455

Patent

active

054758300

ABSTRACT:
A method and a structure for implementing integrated circuit designs into a plurality of clocked and unclocked reprogrammable logic circuits. Software structures analyze the target logic circuit, form clusters, partition the integrated circuit design and implement the partitions into the clocked and unclocked reprogrammable logic circuits in order to prevent hold time violation artifacts.

REFERENCES:
patent: 4020469 (1977-04-01), Manning
patent: 4306286 (1981-12-01), Cocke et al.
patent: 4488354 (1984-12-01), Chan et al.
patent: 4503386 (1985-03-01), DasGupta et al.
patent: 4577276 (1986-03-01), Dunlop et al.
patent: 4642487 (1987-02-01), Carter
patent: 4697241 (1987-09-01), Lavi
patent: 4744084 (1988-05-01), Beck et al.
patent: 4752887 (1988-06-01), Kuwahara
patent: 4777606 (1988-10-01), Fournier
patent: 4823276 (1989-04-01), Hiwatashi
patent: 4873459 (1989-10-01), El Gamal et al.
patent: 4908772 (1990-03-01), Chi
patent: 4914612 (1990-04-01), Beece et al.
patent: 4937827 (1990-06-01), Beck et al.
patent: 4942536 (1990-07-01), Watanabe et al.
patent: 4965739 (1990-10-01), Ng
patent: 5003487 (1991-03-01), Drumm et al.
patent: 5036473 (1991-07-01), Butts et al.
patent: 5093920 (1992-03-01), Agrawal et al.
patent: 5109353 (1992-04-01), Sample et al.
patent: 5140526 (1992-08-01), McDermith et al.
patent: 5172011 (1992-12-01), Leuthold et al.
patent: 5259006 (1993-11-01), Price et al.
Odawara, "Partitioning and Placement Technique for CMOS Gate Arrays," IEEE Transactions on Computer Aided Design, May, 1987, pp. 355-363.
Fiduccia et al, "A Linear-Time Heuristic for Improving Network Partitions," IEEE Design Automation Conference, 1982, pp. 175-181.
Schweikert, "A Proper Model for the Partitioning of Electrical Circuits," Bell Telephone Laboratories, Inc., Murray Hill, N.J., pp. 57-62.
"Partitioning of PLA Logic," IBM TDM, vol. 28, No. 6, Nov. 1985, pp. 2332-2333.
McCarthy, "Partitioning Adapts Large State Machines to PLDs," EDN, Sep. 17, 1987, pp. 163-166.
Hennessy, "Partitioning Programmable Logic Arrays," undated, pp. 180-181.
DeMicheli et al, "Topological Partitioning of Programmable Logic Arrays," undated, pp. 182-183.
Munoz et al, "Automatic Partitioning of Programmable Logic Devices,"VLSI Systems Design, Oct. 1987, pp. 74-86.
Geoffrey Mott et al, "The Utility of Hardware Accelerators in the Design Environment," Oct. 1985, pp. 62-71, VLSI Systems Design.
Pardner Wynn, "In-Circuit Emulation for ASIC-Based Designs," Oct. 1986, pp. 38-46, VLSI Systems Design.
Nick Schmits, "Emulation of VLSI Devices Using LACs," May 20, 1987, pp. 54-63, VLSI Systems Design.
Gotaro Odawara et al., "Partitioning and Placement Technique for CMOS Gate Arrays," 1987 IEEE, pp. Q15485-Q15491.
William S. Carter et al., "A User Programmable Reconfigurable Logic Array," 1986 IEEE, pp. 233-235, Custom Integrated Circuits Conference.
Palesko, et al, "Logic Partitioning for Minimizing Gate Arrays", IEEE Transactions On Computer-Aided Design of Integrated Circuits And Systems, vol. CAD-2, No. 2, Apr. 1983.
Daniel K. Beece, "The IBM Engineering Verification Engine," 1988, pp. 218-224, 25th ACM/IEEE Design Automation Conference.
Prathima Agrawal, "A Hardware Logic Simulation System," Jan. 1980, pp. 19-29, IEEE Transactions On Computer Aided Design, vol. 9, No. 1.
Steven Siegel et al, "The Design of a Logic Simulation Accelerator," Oct. 1985, pp. 76-86, VLSI Systems Design.
Gregory F. Pfister, "The Yorktown Simulation Engine: Introduction," 1982 IEEE, pp. 51-54, 19th Design Automation Conference.
Frank B. Manning, "An Approach to Highly Integrated, Computer-Maintained Cellular," Jun. 1977, pp. 536-552, IEEE Transactions on Computers, vol. 26, No. 6.
Jim Donnell, "Crosspoint Switch: A PLD Appraoch," Jul. 1986, pp. 40-44, Digital Design.
M. Abramovici et al, "A Logic Simulation Machine," 1982 IEEE, pp. 65-73, 19th Design Automation Conference.
E. Kronstadt et al, "Software Support for the Yorktown Simulation Engine," 1982 IEEE, pp. 60-64, 19th Design Automation Conference.
Monty M. Denneau, "The Yorktown Simulation Engine," 1982 IEEE, pp. 55-59, 19th Design Automation Conference.
Jorn Garbers et al., "Finding Clusters in VLSI Circuits," IEEE, pp. 520-523.
Alfred E. Dunlop et al., "A Procedure for Placement of Standard-Cell VLSI Circuits," 1985 IEEE, pp. 92-98.
C. M. Fiduccia et al., "A Linear-Time Heuristic for Improving Network Partitions," 1982 IEEE, pp. 175-181, 19th Design Automation Conference.
Balakrishnan Krishnamurthy, "An Improved Min-Cut Algorithm for Partitioning VLSI Networks," May 1984, pp. 438-446, IEEE Transactions on Computers, vol. c-33, No. 5.
Andrew B. Kahng, "Fast Hypergraph Partition," pp. 762-666, 26th ACM/IEEE Design Automation Conference.
Mark R. Hartoog, "Analysis of Placement Procedures for VLSI Standard Oil Cell Layout," pp. 314-319, 23rd Design Automation Conference.
Ronald R. Munoz et al., "Automatic Partitioning of Programmable Logic Devices," Oct. 1987, pp. 74-87, VLSI Systems Design.
Clive McCarthy, "Partitioning Adapts Large State Machines to PLDs," Sep. 17, 1987, pp. 163-166, EDN.
Sharad Malik et al, "Combining Multi-Level Decomposition and Topological Partitioning for Plas," 1987 IEEE, pp. 112-115.
Yen-Chuen Wei et al., "Ratio Cut Partitioning for Hierarchial Designs," pp. 1-24.
Wolfgang Rosenstiel, "Optimizations in High Level Synthesis," 1986, pp. 347-352, Microprocessing and Microprogramming.
Chet A. Palesko et al., "Logic Partitioning for Minimizing Gate Array," Apr. 1983, pp. 117-121, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-2, No. 2.
Giovanni De Micheli et al., "Topological Partitioning of Programmable Logic Arrays," pp. 182-183.
Ching-Wei Yeh et al., "A General Purpose Multiple Way Partitioning Algorithm," pp. Q15400-Q15405.
Yen-Chuen Wei et al., "Towards Efficient Hierarchial Designs by Ratio Cut Partitioning," 1989 IEEE.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Structure and method for providing a reconfigurable emulation ci does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Structure and method for providing a reconfigurable emulation ci, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Structure and method for providing a reconfigurable emulation ci will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1368155

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.