Static information storage and retrieval – Radiant energy
Reexamination Certificate
1999-12-29
2001-10-02
Phan, Trong (Department: 2818)
Static information storage and retrieval
Radiant energy
C365S112000
Reexamination Certificate
active
06297984
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits that are fabricated using plasma processing, such as plasma metal etch, plasma contact/via etch, plasma resist ash, and plasma enhanced chemical vapor deposition (PECVD). More specifically, the present invention relates to a structure and method used to shunt undesirable potentials generated in antenna electrodes during plasma processing.
RELATED ART
Flash EPROM and EEPROM memory devices typically include memory cells, each having diffused source and drain regions formed in a semiconductor substrate, and a floating gate structure (e.g., polysilicon and/or oxide-nitride-oxide (ONO)) that is formed on a gate oxide structure and located over a channel region extending between the source and drain regions. In an erased state, the floating gate stores a neutral charge that permits current flow between the source and drain regions of the memory cell. In a programmed state, the floating gate stores a negative charge that prevents current flow between the source and drain regions of the memory cell. During normal operation, programming/erasing of the floating gate are performed by injecting/drawing-off electrons and holes into/from the floating gate.
Flash EPROM and EEPROM memory devices typically include word lines located over the floating gate of each memory cell arranged in a row. These word lines provide control signals that are applied to associated floating gates during read, program, and erase operations of the memory cells. During these read, program, and erase operations, corresponding control signals are also transmitted to source and/or drain regions of the memory cells either through, for example, diffused bit lines or through metal conductors that are connected to the diffused source/drain regions by metal contacts that extend through a dielectric layer. In some cases, the diffused bit lines form source/drain regions of a column of memory cells.
Plasma processing, including plasma metal etch, plasma contact/via etch, plasma resist ash, and PECVD processes, is used during various stages of integrated circuit fabrication. For example, PECVD is often used to form a SiO
2
layer over the metal lines of integrated circuits. The plasma, or glow discharge, that is generated during plasma processing is produced by the application of a radio frequency (RF) field to a low pressure gas, thereby creating free electrons within the discharge region. In the case of PECVD, these free electrons collide with gas molecules to ionize the reactant gases and form energetic species that adsorb on the upper surface of an underlying wafer, thereby forming the SiO
2
layer.
During plasma processing, a partially-formed integrated circuit is subjected to potentials generated in the plasma by the free electrons and ions. While the bulk substrate of the integrated circuit is charged to a mean potential, the surface of the substrate is subjected to non-homogeneous local potentials that are caused by magnetic and electrostatic fields. In most cases, these magnetic and electrostatic fields are essentially stationary, thereby causing constant charging in regions of the wafer surface located in these electrostatic fields. Problems occur when the constant charging produces built-up potentials that, for example, exceed the programming (disturb) voltage of a floating gate structure, or force high currents through gate oxide structures in CMOS memory devices. In floating gate devices that include ONO structures, these excessive programming voltages can produce permanent charges in the ONO structures that is difficult to remove using “normal” erase procedures (i.e., the procedures designed to remove expected charges from the floating gate), or using non-destructive thermal treatment. In CMOS memory devices, high currents forced through the gate oxide structures result in oxide degradation that can lead to leakage current, and possible gate oxide breakdown.
What is needed is a structure and method that prevents undesirable potentials during plasma processing that produces undesirable ONO charges and gate oxide damage in flash EPROM, EEPROM, and CMOS ICs.
SUMMARY
The present invention is directed to a structure and method for preventing built-up word line and bit line potentials caused by plasma processing during the fabrication of an integrated circuit. In accordance with the present invention, a shunt transistor is connected between each word/bit line (elongated conductor) and ground, and a light sensitive element is connected to the gate of each shunt transistor. During plasma processing, the plasma glow causes the light sensitive element to generate a voltage that is applied to a gate of one or more shunt transistors. Consequently, the built-up potentials in the word/bit lines are shunted to ground throughout the plasma process, thereby preventing high metal/polysilicon line voltages that can charge/damage the floating gates and/or gate oxide structures of the integrated circuit.
In accordance with an embodiment of the present invention, the integrated circuit includes an array of cells arranged in rows and columns on a semiconductor substrate, elongated conductors (e.g., word lines) extending over the rows of memory cells, and a protection circuit located along a peripheral edge of the array. Each cell includes a diffused source region, a diffused drain region, a gate oxide structure formed over a channel located between the source and drain regions, and a gate structure formed on the gate oxide region. The word lines are electrically coupled (i.e., either directly connected or by capacitive coupling) to the gate structures of one row of the cells.
The protective circuit includes shunt transistors connected between the ends of each word line and a ground plate, and one or more light sensitive elements connected to the gates of the shunt transistors. In one embodiment, the light sensitive element includes a first photodiode connected between ground and the gate of the shunt transistor, and a second photodiode connected between the gate of the shunt transistor and the word line. A light shield covers the first photodiode, and the second photodiode is exposed to the plasma glow during the plasma process. In another embodiment, the light sensitive element is a solar cell that is connected between ground and the gate of the shunt transistor.
In another embodiment of the present invention, a method of producing integrated circuits includes forming a plurality of cells and a protection circuit on a substrate, forming an elongated conductor (e.g., metal word line) that extends over and is electrically coupled to the cells and connected to the protection circuit, and then performing a plasma process (e.g., forming an SiO
2
layer over the metal line using a PECVD process). The protective circuit includes a shunt transistor connected between the elongated conductor and ground, and a light sensitive element that is activated by the plasma glow generated during the plasma process to turn on the shunt transistor. By shunting the elongated conductor to ground during the plasma process, high voltages are prevented from being generated in the metal line during the plasma process, thereby protecting the cell from damage.
The novel aspects of the present invention will be more fully understood in view of the following description and drawings.
REFERENCES:
patent: 4800288 (1989-01-01), Inagaki et al.
patent: 4864538 (1989-09-01), Buzak
patent: 4896149 (1990-01-01), Buzak et al.
patent: 5517151 (1996-05-01), Kubota
patent: 5883830 (1999-03-01), Hirt et al.
patent: 5900625 (1999-05-01), Baumgartner
Shin et al., “Impact Of Plasma Charging Damage and Diode Protection On Scaled Thin Oxide,” IEEE, p. 3.1-3.4, (1993).
Amerasekera et al., “ESD Protection Design And Applications To Bidirectional Antenna Protection For Sub-5 nm Gate Oxides,” American Vacuum Society, (1997).
Beaver Patrick T.
Bever Hoffman & Harms LLP
Phan Trong
Tower Semiconductor Ltd.
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