Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2002-12-13
2004-11-23
Lee, Eddie (Department: 2811)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S125000, C438S719000, C257S678000, C257S686000, C257S702000, C257S704000, C257S730000
Reexamination Certificate
active
06821812
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
In its broadest sense, this invention relates to a structure and method for mounting a small sample in an opening in a larger substrate. In a specific embodiment, this invention relates to a structure and method for mounting a small sample of an integrated circuit structure in an opening in a larger substrate such as a semiconductor wafer.
2. Description of the Related Art
Each generation of integrated circuit structures comprises ever smaller structures which must be inspected, tested, and measured using next generation inspection and metrology equipment which must be developed concurrently with the development of the integrated circuit structures. To develop such inspection and metrology equipment, it is necessary that such equipment be tested and calibrated using test wafers processed with such next generation technologies. However, such next generation process technologies typically do not yield samples in wafer form, due to the expense of producing such large size samples.
However, it is often possible to use such next generation technologies to produce small samples in small volume on an experimental basis. But for these samples to be used in an automated metrology or inspection tool, they need to be mounted on a test wafer, typically about 200 millimeters (mm) to about 300 mm in diameter compared to, for example, a 1-10 mm by 1-10 mm generallyrectangular sample. Such small samples need to be mounted in and on such relatively large wafers in such a waythat they appear to the inspection or metrology tools as though they had been formed directly onto and into the wafer. Mounting requirements are that the small sample be coplanar with the upper surface of the wafer, that the backside and edges of the wafer be intact to preserve the ability to load the wafer using a robotic handler, and that the gap between the sample and the rest of the wafer be as small as possible. This is particularly important for CD-SEM tools, where inappropriate mounting can produce fringe fields that distort the imaging.
In the past, the way a small sample containing new processing technology was mounted in a larger test wafer was to isotropically etch a pocket into a <100> silicon wafer to a depth “t” slightly greater than the thickness or depth of the sample to be mounted. This is shown in prior art
FIGS. 1 and 2
where a semiconductor test wafer
2
is shown formed with an etched opening or pocket
10
therein, having a depth t. and a sample
16
shown secured in opening
10
by an adhesive material
20
.
The problem with this structure and method was that a gap
24
was formed between wafer
2
and sample
16
due to the taper of the sidewalls of opening
10
. The tapered sidewalls of opening
10
were formed due to the anisotropic etch characteristics of the etchant used to form opening
10
in test wafer
2
. Experimentally, it was found that the gap formed between the tapered sidewall of opening
10
and sample
16
by the taper in the sidewalls of sample
16
is about 0.71 t, where t is the depth of opening
10
. This can result in formation of gaps which may be hundreds of micrometers (&mgr;m) wide. For example, when opening
10
is 0.5 mm deep, the gap between sample
16
and the tapered sidewall of opening
10
may be as much as 355 &mgr;m wide, as shown in prior art
FIGS. 1 and 2
. Such a large gap can be seen by the inspection and metrology equipment and has been found to interfere with the testing and calibration of the equipment being developed for the new processing technology.
While it might appear to be simple to merely alter the means used to form the opening, such alterations are also fraught with problems. For example, if a laser were to be used instead of the etchant system to achieve non-tapered walls in opening
10
, loss of depth control of opening
10
in wafer
2
could occur resulting in opening
10
extending completely through wafer
2
. Furthermore, etching a silicon wafer having a <110> upper surface (instead of the <100> upper surface referred to above) would achieve formation of the desirable non-tapered walls in an opening
10
, but that face of silicon cannot be etched to yield a rectangular shaped opening (as viewed from the top of opening
10
). Rather an opening having the cross-section of a parallelogram is formed. Furthermore, even if an opening having non-tapered sidewalls and rectangular in cross-section could be formed, it would be difficult to mount the sample in such an opening (if an adhesive was used), without forming an undesirable gap between the sample and such non-tapered sidewalls.
It would, therefore, be desirable to provide a way of mounting a sample in/on a substrate such as a semiconductor test wafer in a manner which will suppress or avoid formation of gaps adjacent the edge of the sample, which gap, for example, would be visible to inspection and metrology equipment being tested and calibrated.
SUMMARY OF THE INVENTION
The invention, in its broadest sense, comprises a process and structure for mounting a small sample in an opening in a large substrate by using an intermediate size structure. wherein the small sample is mounted in a small opening in the intermediate size structure which then, in turn, is mounted in an intermediate size opening in the large substrate.
In a preferred embodiment the invention comprises a process and structure for mounting a small sample containing integrated circuit structure, such as next generation technology, in an opening in a larger test substrate, such as a semiconductor wafer, without the formation of gaps around the edge of the sample which would be visible to equipment being tested and calibrated. This embodiment of the process is carried out by first mounting the test sample in an opening in a die. The opening in the die is formed completely through the die, and has tapered sidewalls.
The upper surface of the sample directly abuts the edges of the smallest portion of the tapered opening in the die, The die is then, in turn, mounted in a test wafer in an opening with tapered sidewalls in the test wafer. The opening in the die is sized to generally equal, at the smallest end of the tapered sidewalls of the opening, the width and length of the rectangular sample. By placing both the surface of the sample containing the new process technology and the surface of the die adjacent the smallest portion of the tapered sidewall opening down on a common flat surface, the die and the sample may be secured to one another by an adhesive introduced into the gap on the respective rear sides of the die and sample. When the secured together die and sample are then inverted and placed in a larger opening in the test wafer, the test equipment does not see any gap between the sample and the die (due to the butting together of the sample and die. The test equipment also does not see any gap between the die and the test wafer (despite the possible existence of a such a gap, depending on the means used to secure the die to the test wafer) because the overall dimensions of the die are preselected to exceed the boundaries of the field of view of the new technology equipment being tested and calibrated.
REFERENCES:
patent: 5563444 (1996-10-01), Leroux et al.
patent: 6413153 (2002-07-01), Molnar
patent: 6461934 (2002-10-01), Nishida et al.
Blanquies René Maurice
Ovtcharov Dimitar
Tortonese Marco
KLA-Tencor Technologies Corporation
Lee Eddie
Magee Thomas
Taylor John P.
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