Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-04-10
2002-03-26
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S198000
Reexamination Certificate
active
06362669
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits, and more particularly to power detection circuits for integrated circuits.
RELATED ART
In order to successfully initialize an integrated circuit (IC) device, the user of the IC device must supply proper power levels as specified by the device's manufacturer. Power-on reset (POR) control circuits are used in many IC devices, such as programmable logic devices (PLDs), to detect when the internal operating voltage of the IC is within this pre-defined proper power level. For example, a POR control signal generated by the POR circuit may be used to reset selected state elements (e.g., flip-flops) of the IC to a known state. In PLDs, the POR control signal is also used to initiate a configuration operation during which configuration data is written to the various programmable logic elements of the PLD.
FIG. 1
is a schematic diagram showing a simplified conventional integrated circuit (IC)
100
that includes a user logic circuit
110
, a conventional power-on reset (POR) circuit
120
, and a configuration circuit
130
. Logic circuit
110
includes a first combinational logic portion LOGIC1, first and second flip-flops FF
1
and FF
2
, and a second combinational logic portion LOGIC2. Combinational logic portions LOGIC1, and LOGIC2 include combinational logic circuits, such as logic gates and inverters. Flip-flops FF
1
and FF
2
have reset (R) terminals connected to receive the POR control signal generated by POR circuit
120
, set (S) terminals connected to receive configuration data transmitted from configuration circuit
130
, data input (D) terminals for receiving data transmitted from combinational logic circuit LOGIC1, and data output (Q) terminals for transmitting state information to combinational logic circuit LOGIC2. POR circuit
120
includes a p-channel transistor
122
, an n-channel transistor
124
, and a pair of inverters
126
and
127
. The input terminal of inverter
127
is connected to a node
128
, which is located between p-channel transistor
122
and n-channel transistor
124
. The POR control signal is generated at the output terminal of inverter
127
. The components of IC device
100
are for explanatory purposes only, and do not necessarily represent a particular IC device.
FIG.
2
(A) and
3
(A) are timing diagrams showing internal voltage V
DD
and the POR control signal, respectively, during an ideal power-up operation of IC device
100
. Referring to FIG.
2
(A), the power-up operation is divided into three parts: a power-up/reset phase (time t
0
to t
1
), a configuration phase (time t
1
to time t
2
), and a normal operation phase (after time t
2
). The power-up/reset phase begins when external power supply is initially applied to IC device
100
, thereby causing internal voltage V
DD
to increase until it reaches a minimum operating voltage (“trip point”) V
PT
. Referring to FIG.
3
(A), during the power-up/reset phase, the high POR control signal causes IC device
100
to reset. Next, referring to FIG.
3
(A), when internal voltage V
DD
reaches minimum voltage V
PT
(at time t
1
), the POR control signal output from inverter
127
(see
FIG. 1
) switches to a low voltage level, thereby initiating the configuration phase. The configuration phase, which begins at time ti, involves writing configuration data into selected state elements (e.g., flip-flops FF
1
and FF
2
; see FIG.
1
). During the configuration phase, V
DD
achieves a stable operating voltage level (e.g., 5 Volts, 3.3 Volts, 2.5 Volts), which is within an operating range V
OP
that is bounded at a lower end by minimum operating voltage V
PT
and at an upper end by a maximum operating voltage V
MAX
. Normal operation is initiated at a time t
2
, which occurs after completion of the configuration operation.
As indicated in FIG.
2
(A), an ideal power-up operation is characterized by a linearly increasing internal voltage V
DD
that passes through minimum voltage V
PT
only one time (e.g., at time t
1
). This ideal power-up operation is difficult to achieve when internal voltage V
DD
is slow to achieve the stable state, or when noise creates power variations when the increasing V
DD
level passes through trip point V
PT
.
FIGS.
2
(B) and
3
(B) are timing diagrams showing internal voltage V
DD
and the POR control signal, respectively, during unstable power-up operations. In particular, minor fluctuations that can occur as internal voltage V
DD
increases above minimum voltage V
PT
(e.g., at times ta through te; see FIG.
2
(B)) cause rapid changes (indicated by spikes
310
in FIG.
3
(B)) in the POR control signal before internal voltage V
DD
reaches the stable operating voltage (shown at time tf in FIG.
2
(B)). These rapid changes in the POR control signal can cause glitches (i.e., erroneous configuration of IC device
100
) that result in malfunction or improper initialization of IC device
100
. Specifically, propagation of the rapidly changing POR control signal throughout IC device
100
can cause the set (configured) state and reset state of flip-flops FF
1
and FF
2
to become out of synchronization, thereby creating an improper configuration state (e.g., with flip-flop FF
1
in a reset condition and flip-flop FF
2
in a configured (set) condition) that results in erroneous operation of IC device
100
.
What is needed is a POR circuit that eliminates glitches in the POR signal that are caused by unstable power-up operations.
SUMMARY
The present invention is directed to a power-on reset (POR) circuit that controls a POR control signal in an IC device such that, when unstable power levels are detected, the POR control signal is maintained in an asserted condition until the IC device is fully reset, thereby preventing glitches (i.e., erroneous configuration of the IC device) that can occur with conventional POR circuits (described above). During a start-up phase of the IC device operation, the POR control circuit maintains the POR control signal in the asserted condition for a first delay period whose length is determined, in part, by the amount of noise in the applied power signal. By maintaining the POR control signal in the asserted condition until the applied power achieves a steady state, glitches caused by rapid assertion and de-assertion of the POR control signal in response to noisy start-up conditions are prevented. After the internal voltage of the IC device achieves a steady state for a suitable period of time, the POR control circuit de-asserts the POR control signal, thereby initiating configuration of the IC device. Subsequently, if a low power condition is detected, the POR control circuit asserts the POR control signal, and maintains the POR control signal in the asserted condition for a pre-defined delay period after the low-power event is detected, thereby allowing the IC device to fully reset.
In accordance with an embodiment of the present invention, a POR circuit includes a detector circuit and a control circuit. The detection circuit generates a detection signal having a first voltage level when an internal voltage level of the IC device is less than a predefined voltage level, and a second voltage level when the internal voltage level is greater than the pre-defined voltage level. The control circuit asserts and de-asserts the POR control signal in response to changes in the detection signal. Specifically, the POR control circuit includes an one-shot delay circuit connected in parallel with a power-up delay circuit that maintain the POR control signal in an asserted state for respective delay periods after the detection signal indicates a low-power event, thereby delaying configuration until the IC device is fully reset.
The present invention will be more fully understood in view of the following description and drawings.
REFERENCES:
patent: 5177375 (1993-01-01), Ogawa et al.
patent: 5180926 (1993-01-01), Skripek
patent: 5436586 (1995-07-01), Miyamoto
patent: 5467039 (1995-11-01), Bae
patent: 5767710 (1998-06-01), Cho
patent: 5936444 (1999-08-01), Pathak et al.
patent:
Lo Jack Siu Cheung
Zhou Shi-dong
Bever Patrick T.
Harms, ESQ Jeanette S.
Tra Quan
Tran Toan
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