Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2008-04-09
2009-12-08
Tran, Minh-Loan T (Department: 2895)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S629000, C438S735000, C257S774000, C257SE21585, C257SE23145, C257SE23151
Reexamination Certificate
active
07629264
ABSTRACT:
The present invention in one embodiment provides a method of forming an interconnect comprising, providing a interlevel dielectric layer atop a substrate, the interlevel dielectric layer including at least one tungsten (W) stud extending from an upper surface of the interlevel dielectric to the substrate; recessing an upper surface of the at least one tungsten (W) stud below the upper surface of the interlevel dielectric to provide at least one recessed tungsten (W) stud; forming a first low-k dielectric layer atop the upper surface of the interlevel dielectric layer and the at least one recessed tungsten (W) stud; forming a opening through the first low-k dielectric layer to expose an upper surface of the at least one recessed tungsten stud; and filling the opening with copper (Cu).
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Bonilla Griselda
Clevenger Lawrence A.
Grunow Stephan
Kumar Kaushik A.
Petrarca Kevin S.
International Business Machines - Corporation
Li, Esq. Wenjie
Scully , Scott, Murphy & Presser, P.C.
Sun Yu-Hsi
Tran Minh-Loan T
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