Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-08-21
2002-10-22
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S189070, C365S203000, C365S210130
Reexamination Certificate
active
06469929
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory arrays, and particularly to a structure and method for high speed sensing of memory arrays.
2. Description of the Related Art
Various types of memory cells are known in the art. In general, a memory cell stores a binary digit, i.e. a logic one or a logic zero. A volatile memory cell requires a DC current to retain its logic state. Volatile memory cells can include, for example, a dynamic random access memory (RAM) that stores its logic state as a charge on a capacitor or a static RAM that includes a bi-stable flip-flop to store its logic state. A non-volatile memory cell retains its logic state even if the DC current fails. Non-volatile memory cells can include, for example, a read only memory (ROM) that includes a floating gate. This floating gate can be charged, thereby altering the threshold voltage of the memory cell. Specifically, if a floating gate of the ROM has not been charged (i.e. the memory cell is un-programmed), then the ROM has a corresponding low threshold and will turn on when selected. If the floating gate of the ROM has been charged (i.e. the memory cell is programmed), then the ROM has a corresponding high threshold and will not turn on when selected. The un-programmed and programmed memory states typically represent logic zero and logic one, respectively, of the ROM.
FIG. 1
illustrates a memory array
100
including a plurality of ROM memory cells M(R,C), wherein R refers to the row of the array and C refers to the column of the array. To read the state of a memory cell M (also called “sensing” herein), the word line WL coupled to the control gate of the memory cell M, the bit line BL coupled to the source of the memory cell M, and the bit line BL coupled to the drain of the memory cell M are selected. Specifically, for example, to sense memory cell M(
3
,
2
), a read voltage is applied to word line WL
3
, bit line BL
3
is grounded, and bit line BL
2
is coupled to a sense amplifier (not shown).
Note that all other word lines, i.e. word lines WL
1
, WL
2
, WL
4
, and WL
5
, are coupled to ground (closed) and all other bit lines, i.e. BL
1
, are left floating. In this manner, deselected memory cells not in the same row as M(
3
,
2
) cannot conduct because these deselected memory cells do not receive the read voltage on their gates. Moreover, deselected memory cells in the same row as the selected cell have floating drains and sources, thereby also preventing these deselected memory cells from conducting. Thus, only memory cell M(
3
,
2
) has the potential to conduct.
In a typical embodiment, the sense amplifier provides a pull-up voltage on selected bit line BL
2
(called a charging operation). In this configuration, if memory cell M(
3
,
2
) is programmed, then this memory cell will not conduct. Therefore, the voltage on bit line BL
2
would remain substantially at the pull-up voltage provided by the sense amplifier. If memory cell M(
3
,
2
) is un-programmed, then this memory cell will conduct, thereby pulling the voltage on bit line BL
2
to ground. The sense amplifier can detect the voltage level on bit line BL
2
, typically by comparing it to a reference voltage, thereby allowing the state of memory cell M(
3
,
2
) to be read.
In a typical memory array, each bit line BL is connected to many memory cells M. Therefore, these bit lines have large associated parasitic capacitances. The higher the capacitance, the longer the time required to charge the selected bit line coupled to the sense amplifier. Unfortunately, charging the bit line too fast can result in overcharging, thereby undesirably lengthening the time to read the selected memory cell. Therefore, a need arises for a structure and method for quickly and efficiently charging the bit line, thereby allowing high speed sensing of the memory cell.
SUMMARY OF THE INVENTION
In accordance with the present invention, a system for sensing the state of a memory cell includes both dynamic and static clamping of the bit line coupled to the memory cell. This dual clamping configuration/operation ensures a quick charge of the bit line while eliminating overcharging of the bit line. In this manner, sensing the state of the memory cell is substantially independent of the size of the memory array.
In accordance with one embodiment, a sensing system for sensing the state of a memory cell includes a system bit line coupled to a terminal of the memory cell, a charge initiation device for activating a charge operation on the system bit line, and a control unit connected between the system bit line and the charge initiation device. The control unit includes a first circuit to charge the system bit line to a first predetermined voltage and a second circuit to charge the system bit line to a second predetermined voltage.
The first circuit includes a static clamp that charges the system bit line to a voltage defined by VB−VTN, wherein VB is a bias voltage and VTN is the threshold voltage of an n-type transistor. In one embodiment, the static clamp includes a first n-type transistor having a source coupled to the memory cell, a drain connected to the charge initiation device, and a gate receiving the bias voltage VB, wherein the bias voltage VB is defined by VTN<VB<VBLD+VTN, wherein VBLD is a desired voltage on the system bit line.
The second circuit includes a dynamic clamp that charges the system bit line from VB−VTN to VBLD. In one embodiment, the dynamic clamp includes a first p-type transistor having a source connected to the charge initiation device, a drain coupled to the memory cell, and a gate receiving a signal derived from a voltage on the system bit line. The dynamic clamp further includes a comparator receiving the voltage on the system bit line and a reference voltage, and outputting the signal derived from the voltage on the system bit line. In one embodiment, the reference voltage is equal to the desired bit line voltage.
The sensing system can further include a sense amplifier coupled to the charge initiation device. In one embodiment, the sense amplifier compares the current through the system bit line with a current through a reference system bit line. In this embodiment, the reference system bit line is coupled to a terminal of a reference memory cell. A reference charge initiation device is connected to the sense amplifier for activating a charge operation on the reference system bit line. Additionally, a reference control unit is connected between the reference system bit line and the reference charge initiation device, wherein the reference control unit includes a first reference circuit to charge the reference system bit line to the first predetermined voltage and a second reference circuit to charge the reference system bit line to the second predetermined voltage.
In accordance with one feature of the present invention, the sense amplifier can include a first stage for sensing a first current through the system bit line and a second stage for generating a first derived current from the first current. The first stage can include a first n-type transistor having a gate and a drain connected to a supply voltage and a first p-type transistor having a source connected to the supply voltage, and a gate and a drain connected to a source of the first n-type transistor and the charge initiation device. The second stage can include a second p-type transistor having a source connected to the supply voltage, a gate connected to the gate of the first p-type transistor, and a drain connected to an amplifier circuit.
The sense amplifier can further include a first reference stage for sensing a first reference current through the reference system bit line, wherein the second stage generates a second derived current from the first reference current. The first reference stage can include a first reference n-type transistor having a gate and a drain connected to the supply voltage and a first reference p-type transistor having a source connected to the supply voltage, and a gate and a drain connect
Dadashev Oleg
Kushnarenko Alexander
Bever Hoffman & Harms LLP
Elms Richard
Harms Jeanette S.
Nguyen Van-Thu
Tower Semiconductor Ltd.
LandOfFree
Structure and method for high speed sensing of memory arrays does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Structure and method for high speed sensing of memory arrays, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Structure and method for high speed sensing of memory arrays will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2957870