Structure and method for fabrication of field effect...

Semiconductor device manufacturing: process – Forming schottky junction – Using refractory group metal

Reexamination Certificate

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C438S571000, C438S618000, C438S685000, C257SE21240, C257SE21374, C257SE21400

Reexamination Certificate

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08003504

ABSTRACT:
A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.

REFERENCES:
patent: 2006/0223293 (2006-10-01), Hwang et al.
patent: 2007/0018198 (2007-01-01), Brandes et al.
patent: 2008/0224184 (2008-09-01), Shannon et al.
Karmalkar, et al., “Enhancement of Breakdown Voltage in AlGaN/GaN High Electron Mobility Transistors Using a Field Plate,” IEEE Transactions on Electron Devices, vol. 48, No. 8, pp. 1515-1521, Aug. 2001.
Wu, et al., “30-W/mm GaN HEMTs by Field Plate Optimization,” IEEE Electron Device Letters, vol. 25, No. 3, pp. 117-119, Mar. 2004.
Wu, et al., “High-gain Microwave GaN HEMTs with Source-terminated Field-plates,” IEEE IEDM Technical Digest, pp. 1078-1079, Dec. 2004.

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