Structure and method for embedding capacitors in z-connected...

Details Structure and method for embedding capacitors in z-connected... Structure and method for embedding capacitors in z-connected...

2007-04-03

2007-04-03

Reichard, Dean A. (Department: 2841)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C361S763000

Reexamination Certificate

active

10840920

ABSTRACT:
A chip module element having an array of capacitors, a planar interconnect structure coupled to the array of capacitors, and a multilayer circuit structure coupled to the planar interconnect structure. The planar interconnect structure includes a plurality of conductive elements (e.g., z-connections and conductive posts) electrically communicating the capacitors and the multilayer circuit structure. A plurality of conductive pins is coupled to the multilayer circuit structure. The array of capacitors is capable of being charged by providing an electrical current which passes from the pins, through the multilayer circuit structure, through the conductive elements, and to the capacitors. A method for making a chip module element comprising forming an array of capacitors, electrically testing the capacitors in the array to determine which capacitors are defective and which are acceptable, and storing data of the defective capacitors in an information storage medium. The method further includes forming an interconnect structure on the array of capacitors, wherein the interconnect structure includes a plurality of conductive elements, and wherein the conductive elements are electrically coupled to the acceptable capacitors.

REFERENCES:
patent: 4652977 (1987-03-01), Jones
patent: 5502397 (1996-03-01), Buchanan
patent: 6388207 (2002-05-01), Figueroa et al.
patent: 6552696 (2003-04-01), Sievenpiper et al.
patent: 6791846 (2004-09-01), Smith et al.
patent: 2001/0032738 (2001-10-01), Dibene et al.

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