Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-11-13
2004-07-06
Zarneke, David A. (Department: 2827)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C438S006000, C438S010000, C438S014000, C438S015000
Reexamination Certificate
active
06759257
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to embedded capacitors. More particularly, the present invention provides a structure and method for embedding capacitors in multi-chip modules.
2. Description of the Prior Art
A bypass capacitor safeguards a power system from signal induced fluctuation by supplying a reservoir of charge on multi-chip modules (MCMs) in close proximity to semiconductor chips. Currently high performance mainframe computers utilize hundreds of surface mounted LICAs (Low Inductance Capacitor Arrays) on MCMs in close proximity to semiconductor chips. These LICAs consume valuable area on MCMs and currently cost from approximately $3 to about $10 each.
As MCMs frequencies increase, parasitic series inductances in the LICAs increase and the utility of LICAs as bypass capacitors decreases. When the series inductance increases, the capacitors ability to rapidly supply charge to a semiconductor chip over a given distance diminishes. Furthermore, the distance from switching drivers at the center of a semiconductor chip is sufficiently far from the LICA capacitors that the flight time prevents these capacitors from attenuating the early switching noise at the high frequencies. As frequencies increase to ~1 GHz the impedence of the parasitic inductance increases to the point that it dominates the LICA component performance. Thus, LICAs may have limited utility beyond a frequency of about 1 GHz.
Recognizing that the inductances and distances between the LICAs and a chip are greater than the inductances and thickness of thin film MCMs, a solution to the bypass capacitor problem at GHz frequencies is to embed thin film capacitors within thin film MCMs. Such a solution can provide high frequency (>1 GHz) performance and open up more area for additional active components on MCMs.
When using a buildup process to make an MCM, some defects in embedded thin film capacitor layers are likely to occur. Such defects could become power to ground shorts that render the MCM useless. In order to avoid such an occurrence, one would like to be able to test all capacitors prior to connecting them up to the subsequent build up layers. This is very difficult in build-up structures without having a separate mask available for every conceivable combination of good and defective capacitors. For a large number of capacitors, such a multi-mask approach becomes very impractical. Therefore, what is needed and what has been invented is a structure and method which overcome the foregoing difficulties.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide a method for making a chip module element comprising forming an array of capacitors; electrically testing the capacitors in the array to determine which capacitors are defective and which are acceptable; and storing data of the defective capacitors in an information storage medium. The method further comprises forming an interconnect structure on the array of capacitors, wherein the interconnect structure includes a plurality of conductive elements (e.g., conductive posts and z-connections) and wherein the conductive elements are electrically coupled to the acceptable capacitors. The forming of an interconnect structure comprises forming the plurality of conductive elements using at least one of the following procedures: sputtering, electroless plating, or electrolytic plating. The forming of an interconnect structure may alternatively include laminating an adhesive bonding sheet on the array of capacitors; forming a plurality of apertures in the bonding sheet adjacent to the acceptable capacitors; and depositing a conductive material within the apertures. The forming of an array of capacitors may comprise forming an array of capacitors on a silicon substrate.
Embodiments of the present invention further provide a chip module element having an array of capacitors; a planar interconnect structure coupled to the array of capacitors; and a multilayer circuit structure coupled to the planar interconnect structure. The interconnect structure comprises a plurality of conductive elements (e.g., z-connections and conductive posts) electrically communicating the capacitors and the multilayer circuit structure. A plurality of conductive pins is coupled to the multilayer circuit structure. The array of capacitors is capable of being charged by providing an electrical current which passes from the pins, through the multilayer circuit structure, through the conductive elements, and to the capacitors.
These provisions together with the various ancillary provisions and features which will become apparent to those skilled in the art as the following description proceeds, are attained by the methods and chip module elements of the present invention, preferred embodiments thereof being shown with reference to the accompanying drawings, by way of example only, wherein:
REFERENCES:
patent: 3618201 (1971-11-01), Makimoto et al.
patent: 3813650 (1974-05-01), Hunter
patent: 4309811 (1982-01-01), Calhoun
patent: 5514884 (1996-05-01), Hively et al.
patent: 5817533 (1998-10-01), Sen et al.
patent: 6410356 (2002-06-01), Wojnarowski et al.
patent: 6514779 (2003-02-01), Ryu et al.
McCormack Mark Thomas
Peters Mike
Fujitsu Limited
Sheppard Mullin Richter & Hampton LLP
Zarneke David A.
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