Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor
Reexamination Certificate
2002-10-22
2004-02-24
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with field effect transistor
C257S134000
Reexamination Certificate
active
06696706
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
Embodiments of the present invention relate to the field of junction field effect transistors (JFETs). More particularly, embodiments of the present invention relate generally to a JFET with reduced junction gate capacitance.
2. Related Art
Junction field effect transistors (JFETs) are majority carrier devices that conduct current through a channel that is controlled by the application of a voltage to a p-n junction. The JFET semiconductors may be constructed as p-channel or n-channel devices and may be operated as enhancement mode devices or depletion mode devices.
The most common JFET semiconductor is the depletion mode type. The depletion mode device is a normally “on” device that is turned off by reverse biasing the p-n junction so that pinch-off occurs in the conduction channel. For example, p-channel depletion mode devices are turned off by the application of a positive voltage (+VGS) between a gate and source region. Alternatively, n-channel depletion mode devices are turned off by the application of a negative voltage between (−VGS) between a gate and source region.
Enhancement mode, or normally “off” JFETs are characterized by a channel that is sufficiently narrow such that a depletion region at zero applied voltage extends across the entire width of the channel. Application of a forward bias reduces the width of the depletion region in the channel, thereby creating a conduction path in the channel. A p-channel enhancement mode JFET is turned on by the application of a negative voltage (−VGS) between a gate and source region. Alternatively, n-channel enhancement mode JFETs are turned on by the application of a positive voltage (+VGS). The input voltage of an enhancement mode JFET is limited by the forward breakdown of the p-n junction.
The JFET transistor can be implemented within modern electronic circuit applications that frequently require DC power supplied at regulated voltage levels to a microprocessor. For example, in the area of low voltage and high current applications, DC to DC converters, such as, voltage regulator modules (VRMs), are typically used to maintain the output voltage of a power supply at a constant level. Typical circuits known as DC-DC converters include a buck converter, boost converters, and the buck boost converter, etc.
The next generation of computer microprocessor will operate at significantly lower voltages and higher currents. As such, microprocessors may require highly accurate supply voltage regulations in which the VRM is located on the mother board next to the microprocessor load to increase high power density and to operate at high efficiency. To meet these requirements, the power conversion must be performed at a high switching frequency.
However, higher switching frequency in a power converter is associated with larger switching losses due to large gate to drain capacitance in traditional JFET devices in VRM circuitry. The result is power dissipation in the VRM device with excessive heat generation and a reduction in overall circuit efficiency. Prior Art
FIG. 1
illustrates a semiconductor device
100
including a plurality of n-channel JFETs showing high gate to drain capacitance.
Semiconductor device
100
includes a n
++
substrate
160
that forms a drain region for a plurality of n-channel JFET transistors. An n-type epitaxial layer
120
is disposed on top of the n
++
substrate
120
. A plurality of source regions
130
is formed on a surface of the n-type epitaxial layer
120
. A plurality of gate regions
110
are formed below well regions formed in the n-type epitaxial layer
120
. The spacing between the plurality of gate regions
110
define the n-channel active areas Wg
140
of each of the plurality of JFET devices. A large passive area defined as Wp
150
contributes to the gate to drain junction capacitance of the semiconductor device
100
.
In addition, surrounding each of the plurality of gate regions
110
are depletion regions Td
170
. The depletion regions Td
170
further contribute to the gate to drain p-n junction capacitance of the semiconductor device
100
. In certain cases, up to ninety percent of the planar area between the drain region
160
and the plurality of depletion regions Td
170
forms the gate to drain p-n junction capacitance. This large capacitance deleteriously effects the switching capacity of the semiconductor device
100
, and, as such, the efficiency of VRM circuitry that includes the semiconductor device
100
is reduced.
SUMMARY OF THE INVENTION
Accordingly, various embodiments of the present invention disclose a structure and method for a semiconductor device having a reduced junction gate capacitance. Embodiments of the present invention may reduce the junction capacitance between a gate and drain region of a semiconductor device. Embodiments of the present invention may also enhance the high frequency performance of the semiconductor device.
Specifically, embodiments of the present invention describe an n-channel junction field effect transistor (JFET) comprising a heavily doped n
++
substrate forming a drain region, an epitaxial n layer formed on top of the n
+30
substrate, a control structure comprising a p-type gate region implanted into the epitaxial n layer, a source region sharing a p-n junction with the p-type gate region, and an altered epitaxial region. The altered epitaxial region is formed by implanting either high energy n
−
or p
−
dopants directly below the p-type gate region for enlarging a depletion region surrounding the p-type gate region. The enlarged depletion region reduces the junction capacitance between the p-type gate region and the n
++
substrate.
In addition, embodiments of the present invention describe a p-channel junction field effect transistor (JFET) comprising a heavily doped p
++
substrate forming a drain region, an epitaxial p layer formed on top of the p
++
substrate, a control structure comprising an n-type gate region implanted into the epitaxial p layer, a source region sharing a p-n junction with the n-type gate region, and an altered epitaxial region. The altered epitaxial region is formed by implanting either high energy n
−
or p
−
dopants directly below the n-type gate region for enlarging a depletion region surrounding the n-type gate region. The enlarged depletion region reduces the junction capacitance between the n-type gate region and the p
++
substrate.
Embodiments of the present invention also describe a method for forming n-channel and p-channel JFETs with reduced junction gate capacitance. The method includes forming a epitaxial layer on top of an n
++
substrate, forming a plurality of source regions disposed on top of a surface of the epitaxial layer, forming at least one well region in the epitaxial layer defined on either side by source regions from the plurality of n
+
source regions, forming a gate region surrounding a bottom of the well region in the epitaxial layer, and forming an altered epitaxial region directly below the gate region for extending a depletion region surrounding the gate region. The depletion region is extended into the n-type epitaxial region without compromising an active region of the JFET, thereby reducing the junction gate capacitance between the gate and drain regions.
REFERENCES:
patent: 3381188 (1968-04-01), Zuleeg et al.
patent: 4329773 (1982-05-01), Geipel et al.
patent: 4404575 (1983-09-01), Nishizawa
patent: 4419586 (1983-12-01), Phipps
patent: 4506282 (1985-03-01), Baliga
patent: 4519024 (1985-05-01), Federico et al.
patent: 4523111 (1985-06-01), Baliga
patent: 4645957 (1987-02-01), Baliga
patent: 4700461 (1987-10-01), Choi et al.
patent: 4750023 (1988-06-01), Shannon
patent: 4769685 (1988-09-01), MacIver et al.
patent: 4853561 (1989-08-01), Gravok
patent: 5038266 (1991-08-01), Callen et al.
patent: 5396085 (1995-03-01), Baliga
patent: 5910665 (1999-06-01), Plumton et al.
patent: 5945699
Flynn Nathan J.
Lovoltech Inc.
Quinto Kevin
Wagner , Murabito & Hao LLP
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