Structure and fabrication of vertically integrated CMOS logic ga

Details Structure and fabrication of vertically integrated CMOS logic ga Structure and fabrication of vertically integrated CMOS logic ga

1984-09-24

1987-07-14

Edlow, Martin H.

357 59, 357 237, 357 2314, 357 2311, H01L 2702, H01L 2904, H01L 2978

Patent

active

046806091

ABSTRACT:
A vertically integrated CMOS logic gate has spaced semiconductor layers with control gates located between the layers and insulated from them by gate oxide. Transistors formed in one semiconductor layer are vertically aligned with transistors formed in the other semiconductor layer. Pairs of vertically coincident transistors have common control gates and certain of the pairs have integral drain regions. Transistors in one layer are series connected in an open loop configuration and transistors in the other layer are parallel connected in a closed loop configuration. The logic gate function depends on voltages applied to the common control gates and to the open and closed loops. By the vertical integration, a two-input NAND or NOR gate can be made using less area than that required for two simple MOS transistors.

REFERENCES:
patent: 3967988 (1976-07-01), Davidsohn
patent: 4555721 (1985-11-01), Bansal et al.
Faggin et al., "Silicon Gate Technology", Solid State Electronics, Pergamon Press 1970, vol. 13, pp. 1125-1144.

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