Structure and fabrication method for non-planar memory elements

Details Structure and fabrication method for non-planar memory elements Structure and fabrication method for non-planar memory elements

1999-05-03

2001-06-05

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S393000

Reexamination Certificate

active

06242321

ABSTRACT:

FIELD OF THE INVENTION
This invention pertains to two fabrication methods for forming the dielectric structures in non-planar capacitors and ferroelectric memory cells, and to memory device structures utilizing these fabrication methods.
BACKGROUND OF THE INVENTION
The incorporation of high dielectric constant materials into small geometry capacitors suitable for Gigabit scale DRAM introduces fabrication challenges relating to topography, electrode material patterning, reaction of high-epsilon materials with Si contact and ultimate density/scalability. Similar challenges pertain to the fabrication of ferroelectric memory cells for ferroelectric RAM (FRAM) and other non-volatile RAM (NVRAM). To date, most fabrication strategies for making non-planar memory cells (a category of devices including both capacitors or “dielectric memory cells” and ferroelectric memory cells) is that the dielectric or ferroelectric deposition process be a conformal one which leaves a uniformly thin coating of film over all features of the sample topography. This requirement for a conformal process (such as chemical vapor deposition) tends to limit the use of promising spin-on deposition techniques (such as sol-gel) which have a tendency to gap fill and planarize.
An example of a fabrication method incorporating a sol-gel deposited cell dielectric into a three-dimensional memory device is found in U.S. Pat. No. 5,081,559, issued on Jan. 14, 1992 to Fazan et al. In this method, two electrodes are formed sequentially, prior to sol-gel deposition of the cell dielectric material, and the gap defined by a disposable sidewall spacer.
SUMMARY OF THE INVENTION
This invention describes two fabrication methods for making non-planar capacitors and ferroelectric memory cells, and memory device structures utilizing these fabrication methods. A key feature of these fabrication methods is that the ferroelectric or high-epsilon dielectric material is deposited to completely fill a cavity whose geometrical width is the sole determinant of the thickness of the electrically active portion of the ferroelectric or high-epsilon dielectric layer in the final device. In a first embodiment, the cavity into which the dielectric is deposited is defined by the gap the plate and stack electrodes which are deposited and patterned in a through-mask plating step prior to the deposition of the memory cell dielectric or ferroelectric. This embodiment differs from typical memory cell designs in which at least one of the electrodes is put on after the dielectric or ferroelectric layer. Use of the invention makes it possible, for example, to build non-planar capacitors using relatively inexpensive and more easily developable dielectric deposition processes such as sol-gel. This is particularly advantageous when conformal deposition processes (e.g., CVD) do not exist for the desired dielectric material.
Another advantage of this embodiment of this invention is that pinholes in the dielectric will not lead to shorts between the electrodes, as would be the case if the second electrode were applied to a dielectric layer already in the structure as a coating on the first electrode.
In a second embodiment, the electrode adjacent to the device contact material is deposited after the deposition of the cell dielectric. In this embodiment, (i) the gap filled by the cell dielectric material is first defined by a disposable sidewall spacer, and (ii) the cell dielectric is deposited between the first electrode and a temporary “dummy electrode” which is replaced by the final electrode material after deposition of the cell dielectric. This embodiment has the advantage of minimizing the oxidation and contact material reactions might occur were the final electrode material in place during cell dielectric deposition.
The ferroelectric or high-epsilon dielectric layer structures of the present invention have a thickness that is defined by the width of the cavity or gap into which the dielectric layer is to be deposited. When the dielectric is deposited between the plate and stack electrodes, the electrode height defines the width of the capacitor area, and the perimeter or boundary region between the plate and stack electrodes, which may take any of a number of shapes (circle, oval, hollow cross, etc.), defines the length of the capacitor area.
For an annular capacitor, the effective capacitor area is given by the product of the electrode height and the circumference of the annulus. The dielectric thickness is the same as the gap thickness.
This invention enables the fabrication of non-planar capacitors incorporating dielectrics deposited with nonconformal deposition processes such as sol-gel. This is important because sol-gel processes have a number of advantages over CVD, such as cost, ease of development, and availability for a wider range of dielectric materials. Combined with the electrode fabrication process of the present invention as described below, memory cell fabrication for DRAM, FRAM, and/or NVRAM can be relatively simple and inexpensive.


REFERENCES:
patent: 5081559 (1992-01-01), Fazan et al.
patent: 5122477 (1992-06-01), Wolters et al.
patent: 5142437 (1992-08-01), Kammerdiner et al.
patent: 5335138 (1994-08-01), Sandu et al.
patent: 5389566 (1995-02-01), Lage
patent: 5408130 (1995-04-01), Woo et al.
patent: 5466636 (1995-11-01), Cronin et al.
patent: 5619393 (1997-04-01), Summerfelt et al.
patent: 5825609 (1998-10-01), Andricacos et al.

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