Stripe board dummy metal for reducing coupling capacitance

Details Stripe board dummy metal for reducing coupling capacitance Stripe board dummy metal for reducing coupling capacitance

2007-12-25

2007-12-25

Vinh, Lan (Department: 1765)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257S250000, C257S286000, C257S750000, C438S692000

Reexamination Certificate

active

10189910

ABSTRACT:
Dishing is known to be a problem after CMP of dielectric layers in which the distribution of embedded metal is non-uniform. This problem has been solved by populating those areas where the density of embedded metal is low with unconnected regions that, instead of being uniformly filled with metal, are made up of metallic patterns whose combined area within a given region is about half the total area of the region itself. Two examples of such patterns are a line stripe pattern (similar to a parquet flooring tile) and a checker board pattern. Data is presented comparing the parasitic capacitances resulting from the use of patterns of this type relative to conventional solid patterns. The effect of aligning the regions so as to reduce their degree of overlap with wiring channels is also discussed.

REFERENCES:
patent: 5667923 (1997-09-01), Kanata
patent: 5798298 (1998-08-01), Yang et al.
patent: 5915201 (1999-06-01), Chang et al.
patent: 5924006 (1999-07-01), Lur et al.
patent: 5929528 (1999-07-01), Kinugawa
patent: 2001/0030372 (2001-10-01), Mori et al.

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