String programmable nonvolatile memory with NOR architecture

Details String programmable nonvolatile memory with NOR architecture String programmable nonvolatile memory with NOR architecture

2001-03-20

2002-07-02

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185050

Reexamination Certificate

active

06414875

ABSTRACT:

TECHNICAL FIELD
The present invention refers to a string programmable nonvolatile memory with NOR architecture.
BACKGROUND OF THE INVENTION
As known, many of the characteristics of a nonvolatile memory, such as reading and programming speeds, are determined by the architecture of the memory, as well as by the employed manufacturing process.
At present, extensively used nonvolatile memories have a so-called NAND and NOR architectures.
In NAND memories, groups of memory cells, arranged in series and belonging to distinct memory words, are connected to respective bit lines so as to form strings of cells. One memory word is formed by a plurality of adjacent cells connected to different bit lines, while a word string is formed by a plurality of cell strings. In particular, a word string comprises a number of memory words equal to the number of cells contained in a cell string.
NAND memories are advantageous mainly because they have a low bulk and allow the so-called string programming. In fact, all the cells in a cell string can be programmed by biasing the gate terminal of each cell at a programming gate voltage, and the relevant bit line at a programming drain voltage. In this way, by the Fowler-Nordheim effect, controlled charges reach a floating gate region of each selected cell. Consequently, in a single programming step, byte strings (normally 8 or 16 bytes at a time) may be written. Programming of a NAND memory is therefore very fast.
On the other hand, NAND memories have very long access times and consequently they do not meet the requisites of reading speed currently demanded in most applications. In addition, the manufacture of NAND memories is complex and costly.
In NOR memories, instead, the memory cells belonging to a same column are connected in parallel between a same bit line and ground. In addition, the memory cells belonging to a same memory word have their gate terminals connected together via word lines and can be selected simultaneously for reading or for programming. Row and column decoder circuits allow a memory word to be addressed by selecting a word line and a plurality of bit lines.
As compared to NAND memories, NOR memories have the advantage of having very short access times (thus they are faster during reading), moreover, they can be manufactured using a simpler and less costly fabrication process. However, NOR memories are disadvantageous in that allow only one memory word to be programmed at a time. Thus, it is not possible to perform string programming, and it is necessary to repeat the programming step entirely for each word to be stored in memory. Consequently, NOR memories are slow during programming and are not suited for use in fields in which fast acquisition of a high amount of data is required (as in the case, for instance, of digital photocameras).
SUMMARY OF THE INVENTION
According to the present invention, a string programmable memory with NOR architecture is provided.
A memory having a NOR architecture has a memory array including a plurality of memory cells arranged in rows and columns in NOR configuration, the memory cells arranged on a same row being connected to one of a plurality of word lines; and the memory cells arranged on a same column being connected to one of a plurality of bit lines, and a column decoder.
The column decoder comprises a plurality of selection stages, each of which is connected to respective bit lines and receives first bit line addressing signals. The selection stages comprise word programming selectors controlled by the first bit line addressing signals and supplying a programming voltage to only one of the bit lines of each selection stage. Each selection stage moreover comprises a string programming selection circuit controlled by second bit line addressing signals, thereby simultaneously supplying the programming voltage to a plurality of the bit lines of each selection stage.
The string programming selection circuit comprises a plurality Of bit registers that are loaded, during successive clock cycles, with a plurality of data bits, which are then written, simultaneously, to a plurality of bit lines as previously described. Inasmuch as the loading time of a bit register is significantly faster than the programming time of a memory cell, the time saved by programming a string of words simultaneously far exceeds the time spent loading the registers in preparation for the string programming cycle.


REFERENCES:
patent: 5682389 (1997-10-01), Nizaka
patent: 5777923 (1998-07-01), Lee et al.
patent: 5798547 (1998-08-01), Urai
patent: 5812454 (1998-09-01), Choi
patent: 6304489 (2001-10-01), Iwahashi

Affiliated with

Also associated with

Rating

String programmable nonvolatile memory with NOR architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with String programmable nonvolatile memory with NOR architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and String programmable nonvolatile memory with NOR architecture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2893277