Stride enhancer for high speed memory accesses with line fetchin

Details Stride enhancer for high speed memory accesses with line fetchin Stride enhancer for high speed memory accesses with line fetchin

1991-06-14

1994-07-26

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 3642434, 3642443, 3642624, 395400, G06F 1202, G06F 1208

Patent

active

053332911

ABSTRACT:
A stride enhancer provides high memory bandwidth on strides greater than one and minimizes requests to memory. The basic memory module (BSM) design uses line fetches as the basic cache complex fetch mechanism and allows operation of the BSM to be stride independent. In the preferred implementation, the BSM has two fetch modes; a normal mode and a line fetch mode. In the normal mode, a quadword (QW) is fetched as in the conventional design. In the line fetch mode, all double words (DWs) within the referenced line are returned to the storage control element (SCE) at two DWs per cycle for strides one through eight (twice the conventional bandwidth) or at least one DW per cycle for all other strides (equal to the conventional bandwidth). This is accomplished with two DW busses rather than a single QW bus and by interleaving DW storage locations within the BSM. In line fetch mode for strides one through eight, DWs are read out according to the stride on the two DW busses.

REFERENCES:
patent: 4110822 (1978-08-01), Porter et al.
patent: 4873630 (1989-10-01), Rusterholz et al.
patent: 5179674 (1993-01-01), Williams et al.
patent: 5197002 (1993-03-01), Spencer
patent: 5202972 (1993-04-01), Gusefski et al.

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