Stretching setup and hold times in synchronous designs

Details Stretching setup and hold times in synchronous designs Stretching setup and hold times in synchronous designs

1997-04-17

2001-01-02

Chin, Stephen (Department: 2734)

Pulse or digital communications

Synchronizers

C375S355000, C327S149000, C327S150000

Utility Patent

active

06169772

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to issues arising in synchronous digital circuit designs, and more specifically to a system and method of stretching and decoupling input setup and hold times in synchronous digital circuit designs.
2. Description of Related Art
Increases in clock speeds of synchronous digital designs have increasingly put more constraints on the so-called input “setup” and “hold” times. Generally speaking, collectively the minimum “setup” and “hold” times define the smallest acceptable sampling window in which a synchronous input signal must be stable for correct operation.
To illustrate the magnitude of setup and hold times for a typical synchronous design, the input signals BRDY# (Burst Ready) and RDY# (Bus ready) have a minimum setup time of 5 nanoseconds and minimum hold time of 2 nanoseconds for a five volt, 50 MHz, CX486DX-50 microprocessor from Cyrix Corporation of Richardson, Tex., which is described in the
CX
486
DX/DX
2—3
and
5
Volt Microprocessors Data Book
(order number 94113-01), herein incorporated by reference.
By way of further background, application specific integrated circuits (ASICs) and in particular, microprocessors, have been migrating towards internal clock multiplication so that internal speeds are 2X or greater than the external (bus) clock. For example, the three volt CX486DX2-80 microprocessor from Cyrix Corporation of Richardson, Tex., generates an 80 MHz internal clock from a 40 MHz external clock. The typical way to “clock multiply” the external clock is to drive a phase-locked loop (PLL) having a divide-by-N (e.g. N=2) divider in its feedback loop to produce an N-times higher frequency output clock. While meritorious in the sense that PLLs can converge the phase between the input source clock and the generated clock, known problems with PLLs for clock multiplication applications include, but are not limited to, falling out-of-lock and excessive lock times—making static operation (i.e. stopping the clock) difficult or impossible.
In an improved, but not entirely satisfactory technique for clock multiplication, a higher frequency clock is reconstituted by generating and combining pulse streams skewed in time with respect to another. This is typically accomplished by routing an external clock source through a delay line and selectively combining temporally skewed pulses with the original external clock source. This clock multiplication technique while superior in many respects, may jeopardize setup and hold time requirements since the reconstituted clock is typically skewed from the external clock. Realistically, with such small minimum hold times (i.e. 2 nanoseconds) any significant skew in the reconstituted clock will violate setup and hold time requirements which are specified with respect to the external clock source.
By way of even further background, “synchronizers” are known which are intended to mitigate the so-called “metastable” conditions which can occur in asynchronous systems where the inputs to a latch/flip-flop do not necessarily have a defined temporal relationship with the synchronous clock. By way of illustration, U.S. Pat. Nos. 4,469,964 to Guttag et al. and 4,663,546, to Eitrheim et al. disclose synchronizer circuits for synchronizing an asynchronous input signal with a local “synchronous” clock. Guttag et al. and Eitrheim et al. however, are devoid of any teachings or suggestions of the problems faced in synchronous designs having tight setup and hold times and internally synthesized clocks, which are typically skewed with respect to synchronous external clocks.
It can be seen from the foregoing therefore, that there is a need for a system and method to stretch and decouple setup and hold times in a synchronous digital circuit design, particularly in a system which employs clock multiplication.
SUMMARY OF THE INVENTION
To overcome the limitations of the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a system and method of decoupling and stretching input setup and hold times in a synchronous circuit design.
A feature of the present invention is the capability to use delay line type clock multipliers without regard to the impact of internal clock skew on external input setup and hold times.
Another feature of the present invention is increasing the effective input setup time using the skew of an internally produced clock signal.
These and various other objects, features, and advantages of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and forming a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to the accompanying descriptive matter, in which there is illustrated and described a specific example of a system and method to stretch and decouple setup and hold times in synchronous designs, practiced in accordance with the present invention.


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