Stress testing for semiconductor devices

Details Stress testing for semiconductor devices Stress testing for semiconductor devices

2001-06-28

2003-08-26

Metjahic, Safet (Department: 2171)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

For fault location

Reexamination Certificate

active

06611146

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to electrical stress testing and, more particularly, to stress testing of semiconductor devices.
During the manufacture of semiconductor devices, various types of defects and failures may occur. A failure occurs when a semiconductor device fails to meet its design specifications. A defect occurs when a semiconductor device has an improper structure which may result in an immediate failure of the device, or the device may have the potential to fail during its expected lifetime. For example, due to a manufacturing error, a semiconductor device having a structure such as a metal-insulator-metal (MIM) capacitor may have a latent defect such as thinned electrodes or tiny holes within the insulating material. As a result, the device might sustain a short, a decreased capacitance, or break down over a period of time.
Testing is performed on semiconductor devices in order to locate defects and failures in such devices. Specifically, various populations of devices, such as MIM capacitors, may be subjected to controlled stress test conditions as part of a quality and reliability assurance program for commercial use. During these stress tests, one or more MIM capacitors are typically subjected to a stress test voltage for a predetermined amount of time and at a predetermined temperature. Measurements of stress leakage currents and other parameters are taken to determine breakdown and failure conditions of the devices.
Stress driver circuits are typically used to apply a stress test voltage to the element or elements under test. An input test voltage is applied across buffer circuit elements, such as precision limiting resistors and readback sense circuits which provide information on actual applied voltage and leakage currents. The buffer elements, in turn, are connected to the elements under test. The test voltage is increased or adjusted until the voltage directly across the element(s) under test is precisely equal to the desired stress test voltage. Because resistors and other current carrying elements are used in the test circuitry, however, the voltage across the elements under test is often less than the input test voltage due to a voltage drop as leakage currents are passed through resistive elements. In addition, stress voltages simultaneously applied across a number of test elements may vary from element to element. Without a precise application of test parameters such as stress voltage, it becomes more difficult to fully understand the failure modes of devices subjected to stress conditions.
It is desirable, therefore, to provide a stress testing method and/or apparatus which addresses the abovementioned concerns.
BRIEF SUMMARY OF THE INVENTION
In an exemplary first embodiment of the invention, an apparatus for applying a stress voltage to a device under test includes a stress voltage source, a constant voltage circuit having an input connected to the stress voltage source and an output connected to the device under test. The constant voltage circuit provides a constant stress voltage to the device under test. There is also a control circuit which removes this voltage when the induced leakage current exceeds a predetermined level. A monitoring circuit measures the stress voltage applied to the device under test, and measures leakage current through the device under test. A switch has inputs connected to outputs of the monitoring circuit, with the switch being capable of sending a selected output or outputs of the monitoring circuit to a measurement system. Preferably, the constant voltage circuit is capable of providing a constant voltage source greater than 15 volts.


REFERENCES:
patent: 3552368 (1971-01-01), Hunter
patent: 3640120 (1972-02-01), Nihof et al.
patent: 5686820 (1997-11-01), Riggio
patent: 6262585 (2001-07-01), Frodsham

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