Stress test apparatus and method for semiconductor memory device

Details Stress test apparatus and method for semiconductor memory device Stress test apparatus and method for semiconductor memory device

1997-11-07

1999-10-26

Nelms, David

Static information storage and retrieval

Addressing

365102, 36518517, 36518904, G11C 800

Patent

active

059739819

ABSTRACT:
A stress test apparatus and method for a semiconductor memory device with a plurality of memory cell arrays. The stress test apparatus comprises a plurality of plate terminals connected to one another, each of the plate terminals being connected to a plurality of storage capacitors, first and second switching elements connected in common to the plate terminals, a plate voltage generator connected to the first switching element, a stress signal generator connected to the second switching element, and a switching control signal generator for generating a switching control signal to control the first and second switching elements. According to the present invention, a cell plate voltage is applied and varied to stress the storage capacitors without driving word lines. Therefore, the storage capacitor stressing operation is simply performed, the stress test time is reduced and the cost is cut down.

REFERENCES:
patent: 5255229 (1993-10-01), Tanaka et al.
patent: 5317532 (1994-05-01), Ochii
patent: 5337272 (1994-08-01), Suwa et al.
patent: 5654925 (1997-08-01), Koh

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