Stress relief bend useful in an integrated circuit...

Details Stress relief bend useful in an integrated circuit... Stress relief bend useful in an integrated circuit...

2001-09-18

2003-09-09

Ngo, Hung V. (Department: 2831)

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

C174S251000, C174S254000, C174S260000, C174S261000, C361S773000, C361S776000, C257S669000, C257S674000

Reexamination Certificate

active

06617510

ABSTRACT:

TECHNICAL FIELD
The invention relates to a metallic or an electrical lead terminus with a stress relief portion.
BACKGROUND OF THE INVENTION
A long standing problem know to those skilled in the electronics art involves the mismatch between the thermal properties of material making up an electronic device and the materials making up the substrate to which the device is mounted. Canestaro at al U.S. Pat. No. 4,728,751 addressed the mismatch problem associated with mounting an electronic device, such as a semiconductor chip made primarily of silicon, directly onto an organic substrates, such as printed circuit board made primarily of glass cloth impregnated with epoxy resin or other suitable materials. Canestaro et al solved the mismatch problem by processing a selected surface portion of a substrate to form a relatively low adhesive area surrounded by a relatively high adhesive area. A circuit line pattern was deposited on the substrate, including circuit lines having termini with stress relief bends, located in the relatively low adhesive area on the surface of the substrate. As such, the terminus of each of the circuit lines floats on the surface of the substrate while the remainder of the circuit line is fixed to the relatively high adhesive area on the surface of the substrate. However, the circuit line including the relief bend are co-planar and parallel to the surface of the substrate. Consequently, the lines with the stress relief bend consume a substantial amount of real estate on the substrate.
Ashby, U.S. Pat. No. 3,519,890 also attempted to solve the thermal mismatch problem by interconnecting a microelectronic circuit containing die with a substrate utilizing a meandering conductive line to relieve the stress on the die and conductive line under thermal conditions and temperature cycling. However, the meandering lines did not have a common geometry and as a result took up a substantial amount f valuable area on the mounting substrate.
The present invention provides alternatives to and advantages over the prior art.
SUMMARY OF THE INVENTION
The invention includes a metallic or an electrical trace having a terminus and stress relief bend formed in the trace adjacent the terminus. The stress relief bend is a shaped geometry that has an increased length to distribute strain. The geometry of the bend has the effect of changing the overall elasticity of the trace section (compared to linear sections) thereby limiting strain. The electrical trace may have a portion carried by a flexible substrate to form a flexible circuit. The stress relief bend may be free floating and may extend from the flexible substrate or may be encapsulated by the flexible substrate or other material. The electrical trace and the flexible substrate each have a generally planar portion (extending in the X and Y axes), with the stress relief bend projecting from the plane (along the Z axis). This allows traces to be spaced with a very narrow pitch because the stress relief bend does not take up any valuable real estate on the flexible circuit or the substrate to which the trace is applied.
In the preferred embodiment, the invention included an integrated circuit redistribution patch including an electrical trace having a terminus and stress relief bend adjacent the terminus. The flexible circuit included raised electrical contact features in addition to those utilized to make the termination to the integrated circuit chip. The additional raised electrical contact features allow for electrical connection to input and output (I/O) termination pads on the periphery of the integrated circuit and a higher interconnection site capable of distributing stress.


REFERENCES:
patent: 3519890 (1970-07-01), Ashby
patent: 3785187 (1974-01-01), Wolz
patent: 4640499 (1987-02-01), Hemler et al.
patent: 4728751 (1988-03-01), Canestaro et al.
patent: 5166774 (1992-11-01), Banerji et al.
patent: 5250843 (1993-10-01), Eichelberger
patent: 5469333 (1995-11-01), Ellerson et al.
patent: 5717556 (1998-02-01), Yanagida

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