Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step
Reexamination Certificate
2000-03-16
2001-10-23
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including adhesive bonding step
C438S138000, C438S200000, C438S256000, C156S153000, C257S676000, C436S169000
Reexamination Certificate
active
06306684
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices. In particular, the invention relates to a lead-frame design for integrated circuit packaging to reduce chip stress and deformation and to improve mold filling.
2. Description of Prior Art
The current state of the art for plastic packaged integrated circuits describes an integrated circuit die coupled to a lead frame mounting structure by epoxy, glue or other types of adhesive material. The integrated circuit die and mounting structure are subsequently encapsulated in plastic material, typically through a transfer molding process.
The problem, noticed in the Joint Electron Device Engineering Council (JEDEC) semiconductor package identified as Thin Shrink Small Outline Package (TSSOP), but applicable to virtually all types of plastic encapsulation of integrated circuits, is cracking or fracturing of the integrated circuit die when subject to thermal stress. Thermal stress can, and often does occur, at temperatures above 25 degrees Centigrade. Under test and/or operating conditions, the thermal coefficient of expansion of the mounting structure and the die are not identical. Further, once the device is encapsulated in plastic, the thermal coefficient of expansion of the mounting structure is greater than that of the plastic encapsulant. Under expansion conditions, the plastic encapsulant induces competing and opposite forces on the integrated circuit die. For example, as the temperature increases, either by ambient variation or by operating heat dissipation, the plastic package tends to expand. This expansion induces forces in the integrated circuit die. These forces from the plastic package tend to inhibit the expansion of the die because there are expansion forces from the die itself which are opposite in direction to those of the plastic package. Also, there are expansion forces from the mounting structure which cause a frictional migratory effect on the interface between the die and the die paddle. Above 25 degrees Centigrade, expansion forces occur at two key interfaces as a result of thermal stress: 1) the integrated circuit die and plastic package interface, and 2) the integrated circuit die and mounting structure interface.
The result of these expansion forces typically appears initially as cracks on the bottom of the integrated circuit die, i.e., the surface of the integrated circuit die which interfaces with mounting structure. The cracks or fractures may then propagate throughout the die. Under lower stress conditions, the cracks may be observed on the bottom surface of the integrated circuit die as hairline fractures. These hairline fractures typically result in partial loss of function of the integrated circuit. In extreme cases, the cracks may have propagated throughout the entire thickness of the integrated circuit die to the extent of complete fissure of the die, resulting in loss of function and total failure of the integrated circuit.
Since integrated circuit chip failures due to cracking from thermal expansion is a recognized problem in the industry, the prior art has identified a need to reduce chip stress by redesigning the lead-frame and bonding interface between the chip and lead-frame. With reference to
FIGS. 1A and 1B
, one solution proposed in the prior art is to form grooves
5
or holes
6
in the lead frame or mounting structure
11
. With the groove
5
, the lead frame has a dual plane mounting surface, wherein the top plane
7
is the more substantial plane of the mounting surface. The bottom plane
8
is found at the bottom of the groove
5
and is relatively much smaller in area than the top plane
7
.
The grooves
5
and holes
6
act as expansion joints to relieve stress as the lead frame
11
and die
10
expand and contract relative to each other. With the groove
5
cut in the surface of the lead frame adjacent the integrated circuit die, the thickness of the adhesive between the bottom of the groove
5
and the die is greater than the thickness of the adhesive between the adjacent surface of the lead frame and the die. This additional thickness relieves stress between the two structures in the vicinity of the groove
5
. The holes
6
provide a similar effect.
For example, in U.S. Pat. No. 5,773,878, incorporated herein by reference, a lead-frame having a split die pad is disclosed. The die pad is split into several sections which are joined together by flexible expansion joints. A split die pad allows relative motion between the pad and the chip during die attached cure. The split also breaks down the total die pad area (and length) that is rigidly attached to the chip and to smaller sections. The smaller total die pad area and length reduce the magnitude of the coefficient of thermal expansion between the chip and the die pad, which prevents deformation of the assembly.
An alternative design for a lead-frame or semiconductor element mounting diepad is disclosed in U.S. Pat. No. 5,397,915, incorporated herein by reference. In this reference, a plurality of slits and dimples are disposed on a flat surface of a semiconductor element mounting diepad. The slits penetrate from the face to the back side of the semiconductor element mounting diepad. The slits are formed by punching or chemical etching methods. Slits of the same shape are formed at an interval of the width of the dimples. The rear side is pushed out by press means to form dimples with the boundary of the slits. Thus, the slits are formed in one body at both ends of the dimples. By forming grooves or dimples in the semiconductor element mounting diepad, the contact area with the sealing resin is widened.
In U.S. Pat. No. 5,818,103, incorporated herein by reference, a semiconductor device is described which has a semiconductor chip mounted on the mounting portion of a lead-frame and sealed with a resin. The lead-frame has a groove formed in the lead-frame in a cruciform, radial, lattice or similar pattern capable of reducing thermal stress during intermittent performance test and cycling test while ensuring heat radiation.
In all of the embodiments described in the prior art, the more significant portion of the lead-frame mounting diepad is in contact with the semiconductor chip. If the thermal coefficient of expansion of the mounting structure and the die are not identical, competing and opposite forces are induced in the integrated circuit die sufficient to crack the die. For example, as temperature increases, either by ambient variation or by operating heat dissipation, the mounting structure will expand or contract at a different rate than the integrated circuit die in the plane of the integrated circuit die. While the prior art recognizes a need to relieve this stress, it teaches that significant portions of the mounting structure must remain in contact with the integrated circuit die. Thus, significant localized stress is experienced by the integrated circuit chip.
Therefore, there is a need for a mounting structure or lead-frame design which reduces stress induced by thermal expansion across the entire integrated circuit die as well as local portions of the integrated circuit die.
SUMMARY OF THE INVENTION
The present invention is an alternative design for a lead-frame mounting structure which minimizes the contact area between the lead frame mounting structure and the integrated circuit die. It is now believed that die cracks propagate from silicon defects, like stacking faults, which are found in an integrated circuit die. These defects are found in small areas of the die and have different coefficients of thermal expansion. These small areas are the primary cause of die cracking. The present invention is a lead frame design which allows forces induced by thermal expansion to be spread over larger areas of the die between points of contact with the lead frame. By increasing the distance between points of contact, the force per unit area associated with the defect is reduced and maintained at a level below the fracture point. Since the contact areas between the mount
Fernandez Joseph
Richardson David
Termer Dan
Baker & Botts L.L.P.
Le Vu A.
Luy Pho
Microchip Technology Incorporated
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