Stress isolating signal path for integrated circuits

Details Stress isolating signal path for integrated circuits Stress isolating signal path for integrated circuits

1992-08-12

1993-10-05

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257735, 257741, 257576, 257588, 257777, 257778, 257784, 437182, 437186, 437921, H01L 2904, H01L 2144

Patent

active

052508471

ABSTRACT:
A stress isolating signal path having one end of fixed to a bonding pad of an integrated circuit chip and another end which forms a flexible bonding surface is provided. The flexible bonding surface may be bonded to external package components or external circuitry using conventional wire bond, epoxy bond, tape automated bonding, flip chip bonding, or the like. The signal path is formed using conventional semiconductor thin film deposition, patterning, and etching techniques. The signal path comprises a conductive material compatible with batch semiconductor manufacturing technology.

REFERENCES:
patent: 3487541 (1970-01-01), Boswell
patent: 3588628 (1971-06-01), Peck
patent: 4881117 (1989-11-01), Gandolfi et al.
patent: 4924292 (1990-05-01), Kaufman
patent: 4933743 (1990-06-01), Thomas et al.
patent: 4980753 (1990-12-01), Dunaway et al.
patent: 4990991 (1991-02-01), Ikeda et al.
patent: 4994895 (1991-02-01), Matsuzaki et al.

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