Stress-free shallow trench isolation

Details Stress-free shallow trench isolation Stress-free shallow trench isolation

1998-07-27

2002-03-12

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S435000, C257S510000

Reexamination Certificate

active

06355540

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more especially, to a method for fabricating shallow trench isolation.
2. Description of the Prior Art
For building an integrated circuit operating with desired action, it is necessary to fabricate many active devices on a single semiconductor substrate. Various kinds of devices with different functions, such as transistors, resistors and capacitors, are formed together. Each of the devices on the substrate must be electrically isolated from the others to ensure their individual function. The art of isolating semiconductor devices becomes one important aspect of modern metal-oxide-semiconductor (MOS) and bipolar integrated circuit technology for the separation of different devices or different functional regions. With the high integration of the semiconductor devices, improper isolation among devices will cause current leakage, and the current leakage can consume a significant amount of power. Improper isolation will result in circuit latch-up, which can destroy the circuit temporarily or even permanently. In addition, improper isolation can cause degradation in circuit noise margin, voltage shift and crosstalk.
Local oxidation of silicon (LOCOS) is one of the most well known techniques for isolation. LOCOS provides the isolation by oxidizing the silicon substrate to create silicon dioxide regions among active devices or functional regions. Because it is easy for the silicon substrate to be oxidized into silicon dioxide, LOCOS has the benefits of its process simplicity and low cost, and it becomes the most widely used isolation technique in very large scale integrated (VLSI) circuit. However, with the tendency for the manufacture of semiconductor integral circuit to high package density, LOCOS meets the limitation in its scalability.
The trench isolation, which is usually referred as shallow trench isolation (STI), is another isolation technique developed especially for semiconductor chip with high integration. The trench regions are formed in the semiconductor substrate by recessing the substrate deep enough for isolation and refilling with insulating material to provide the isolation among active devices or different well regions. In general, trench isolation has a better scalability in comparison with LOCOS isolation.
In the paper “Characteristics of CMOS Device Isolation for the ULSI Age” in IEDM Tech. Dig., p. 671, 1994, by A. Bryant, et al., the two different isolation techniques of LOCOS and STI are investigated. The paper reviews how LOCOS and STI isolations are being improved to meet the scaling requirements for abrupt active-isolation transitions, isolation depth, and isolation planarity. For deep sub-micron CMOS generation, the conventional LOCOS isolation suffers from several drawbacks such as large lateral extend of bird's beak, non-planarity, local field oxide thinning effect, and stress-induced silicon defects. The key challenges to LOCOS scaling are insulator thinning at narrow dimension, bird's beak formation, and field-implant encroachment. For future CMOS technology, an effective device isolation method that provides abrupt transitions to active device regions with minimum impact on device characteristics or topography will be required. They come to the conclusions that, at the cost of a trench-fill and planarization, STI is a more direct method of meeting these requirements while benefiting from a significant advantage in planarity.
Trench isolation is developed to be a better isolation technique in deep sub-micron CMOS generation due to the advantages in its scalability, planarity, and isolation depth. But it still encounters several problems such as silicon damage induced by etching and the corner effects. In the paper entitled “Correlation between Gate Oxide Reliability and the Profile of the Trench Top Corner in Shallow Trench Isolation (STI)”, IEDM Tech. Dig., p.747, 1996, T. Park, et al., illustrated three schematic profiles of oxide etch-back trench corners. The gate conductor could wrap around the trench corner when a conventional oxide etch-back process is performed. They propose for above situation a two-step trench etching with a sidewall around. With this two-step trench etching process, the corner parasitic leakage and the gate wrap-around could be solved.
In 1997, T. Park, et al., proposed another method named “very simple trench isolation technology” in their paper “A Very Simple Trench Isolation (VSTI) Technology with Chemo-Mechanically Polished (CMP) Substrate Si” Symposium On VLSI Tech. Dig., p. 121. Based on the idea that the Si wafer is finalized with CMP step, this method provides a simple process to fabricate the isolated trench regions with smaller number of steps compared to the conventional trench isolation technique or even the LOCOS isolation. By this method, low junction leakage current, high breakdown voltage and flat surface can be reached, but the double hump associated with sharp top corner of the active to field boundary could not be completely avoided at a large reverse biased condition.
SUMMARY OF THE INVENTION
A method for fabricating shallow trench regions in a semiconductor substrate is disclosed. Silicon sidewall spacers and a thick thermal oxide film are created at and near the trench corners to prevent the corner effect such as the gate wrap-around and corner parasitic leakage. According to the processes, the trench region is formed with a thermal oxide film on the bottom and the sidewall, a CVD dielectric film on the bottom of the thermal oxide film, and a channel stop region beneath the bottom of the thermal oxide film.
Forming a pad oxide and a silicon nitride layer on a semiconductor substrate, the trench region and active area are defined by a photoresist photolithography followed by an anisotropic nitride etching. After silicon spacers are formed, the semiconductor substrate is recessed to form trench region by another dry etching using the silicon nitride layer and silicon spacers as etching hard mask. A channel stopping implantation is performed. Then a thermal oxide film is regrown on the trench surface to recover the etching damages. After removing the silicon nitride layer, a thick CVD oxide layer, which is formed of TEOS-oxide or BPSG, etc., is deposited on the semiconductor substrate. The oxide film outside the trench regions is removed by using a CMP process. A sacrificial oxide is grown and removed for recovering the polish damages. Finally, the MOS devices are fabricated on the semiconductor substrate by standard processes, and thus complete the present invention.


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