Stress-free shallow trench isolation

Details Stress-free shallow trench isolation Stress-free shallow trench isolation

1998-01-28

2000-02-01

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257510, 257514, 257515, H01L 2900

Patent

active

060206217

ABSTRACT:
A trench isolation in a semiconductor substrate is provided. The trench isolation includes a recessed region in the semiconductor substrate. The trench isolation also has a first insulator layer lining the recessed region. The first insulator aligns with the semiconductor substrate at edge of the recessed region. The trench isolation further includes a second insulator layer filling within the recessed region over the first insulator. As a preferred embodiment, the recessed region can have well rounded corners at bottom and abutting top surface of the semiconductor substrate. The first insulator has inwardly increased height after the planarization process. The second insulator layer aligns with the first insulator at inner edge of the first insulator. The second insulator layer can also have a top plain region.

REFERENCES:
patent: 4839306 (1989-06-01), Wakamatsu
patent: 4952524 (1990-08-01), Lee et al.
patent: 5440166 (1995-08-01), Dixit et al.
patent: 5521422 (1996-05-01), Mandelman et al.
patent: 5830797 (1998-11-01), Cleeves
Andres Bryant et al., Characteristics of CMOS Device Isolation for the ULSI Age, 1994 IEEE, pp. 671-674.
S.E. Kim et al., Nitride Cladded Poly-Si Spacer LOCOS (NCPSL) Isolation Technology for the 1 Giga Bit DRAM, 1996 IEEE, pp. 825-828.
Pierre C. Fazan et al., A Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMs , 1993 IEEE, pp. 57-60.

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