Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-07-06
2002-10-01
Potter, Roy (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S117000
Reexamination Certificate
active
06458622
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to semiconductor components and, more particularly, to stress relief in the semiconductor components.
Semiconductor manufacturers often form conductive bumps on semiconductor chips to electrically contact substrates such as printed circuit boards, Tape Automated Bonding (TAB) substrates, leadframes, etc. Advantages of using conductive bumps include: the ability to perform wafer level packaging, increased Input and Output (I/O) density, which results in a smaller device “footprint,” increased signal propagation speed due to shorter interconnections, reduced vertical profile, and lower device weight.
Typically, the conductive bumps are formed by depositing a layer of masking or stencil material over the substrate, forming openings in the solder mask, disposing a conductive paste in the openings, and reflowing the conductive paste to form the conductive bumps. The semiconductor wafer containing the conductive bumps is then mounted to a support substrate such as a printed circuit board. To prevent damage from mechanical stresses, a stress compensation layer is formed on the semiconductor wafer. In one approach, the stress compensation layer is formed using a resin transfer molding process to encapsulate the surface of the semiconductor wafer. Disadvantages of this technique include air bubble entrapment in the resin and compression of the semiconductor wafer. Another approach incorporates a redistribution dielectric over the surface of the wafer. A disadvantage of this technique is that large bumps must be formed in order to increase the reliability of the package. This results in a low density I/O count due to the large diameter of the conductive bumps.
Accordingly, it would be advantageous to have a semiconductor component that has a photoimageable stress compensation layer. It would be of further advantage for the stress compensation layer to have a Coefficient of Thermal Expansion (CTE) that matches that of solder joints present on the semiconductor component.
REFERENCES:
patent: 6020220 (2000-02-01), Gilleo et al.
Fang Treliant
Keser Lizabeth Ann
Potter Roy
Vo Kim-Marie
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