Stress buffer layer for ferroelectric random access memory

Details Stress buffer layer for ferroelectric random access memory Stress buffer layer for ferroelectric random access memory

2011-01-14

2011-12-06

Potter, Roy (Department: 2822)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Incorporating resilient component

C438S121000, C438S123000

Reexamination Certificate

active

08071430

ABSTRACT:
An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.

REFERENCES:
Manish Ranjan et al., “How buffer layers can provide stress management for wafer-level chip-scale packages,” Solid State Technology, Aug. 2004, http://sst.pennnet.com/display—article/209659/5/ARTCL
one
one/1/How-buffer-layers-can-provide-stress-management-for-wafer-level-chip-scale-packages/,2009 PennWell Corporation, Tulsa, OK, United States.

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