Strapped wordline architecture for semiconductor memory

Details Strapped wordline architecture for semiconductor memory Strapped wordline architecture for semiconductor memory

1998-09-01

1999-08-17

Phan, Trong

Static information storage and retrieval

Format or disposition of elements

365 63, 36523003, 36523006, G11C 502, G11C 506, G11C 800

Patent

active

059403152

ABSTRACT:
Disclosed is a method and apparatus for connecting the wordlines of memory arrays to respective row decoders in a manner which reduces the physical space required for implementing a memory device. The wordlines of a first memory array are connected directly to an adjacent row decoder. Metal straps, which connect across every other wordline of the first memory array, are used to connect the row decoder to the wordlines of another memory array not adjacent to the row decoder. By utilizing the same row decoders for multiple arrays via the metal straps, the number of row decoders required for a memory bank can be reduced, thereby reducing the overall physical space necessary for implementation of the memory device. The use of metal for the straps provides minimal effect on the access timing of the wordlines connected to the row decoders via the metal straps, and the strapping of only every other wordline of each array provides sufficient space between the straps to prevent them from shorting together.

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patent: 5706245 (1998-01-01), Kim
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