Strap resistance using selective oxidation to cap DT poly...

Details Strap resistance using selective oxidation to cap DT poly... Strap resistance using selective oxidation to cap DT poly...

2001-08-13

2003-05-20

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S239000, C438S243000, C438S248000

Reexamination Certificate

active

06566227

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the fabrication of semiconductor integrated circuit (IC) structures, and more particularly to the formation of shallow trench isolation (STI) structures in IC devices.
BACKGROUND
Semiconductor devices are used in a variety of electronic applications, such as personal computers and cellular phones, for example. One such semiconductor product widely used in electronic systems for storing data is a semiconductor memory, and one common type of semiconductor is a dynamic random access memory (DRAM).
A DRAM typically includes millions or billions of individual DRAM cells, with each cell storing one bit of data. A DRAM memory cell typically includes an access field effect transistor (FET) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. In addition, the data charges on the storage capacitor are periodically refreshed during a refresh operation.
Memory devices are typically arranged in an array of memory cells. A source/drain region of the cell access FET is coupled to a bitline, and the other source/drain region is coupled to a plate of a respective storage capacitor. The other plate of the capacitor is coupled to a common plate reference voltage. The gate of the transistor is coupled to a wordline. The storing and accessing of information into and from memory cells is achieved by selecting and applying voltages to the wordlines and bitlines.
In fabricating semiconductor devices such as DRAM's, shallow trench isolation (STI) is a technique used to provide electrical isolation between various element regions.
FIGS. 1-3
illustrate a prior art STI technique used to isolate active areas of a DRAM array. A crystalline silicon
12
substrate covered with a layer of pad nitride
14
(e.g., 200 nm of silicon nitride) is patterned with trenches
13
, e.g. deep trenches, may have areas of crystalline silicon substrate
12
in regions therebetween.
For example, two deep trenches
13
are shown in
FIG. 1
, which may comprise two storage cells or capacitors of a DRAM. An insulating collar
15
is formed within each trench
13
and comprises a thin oxide liner, for example. The trenches
13
are filled with doped polycrystalline silicon (polysilicon)
16
, which is etched back to a depth of, e.g., between 300 to 600 Angstroms below the silicon
12
surface.
Exposed portions of the pad nitride layer
14
and the polysilicon
16
are covered with a nitride frame
18
. The nitride frame
18
may comprise, for example, 20 nm of silicon nitride. A hard mask
20
comprising boron-doped silicon glass (BSG), or alternatively, tetraethoxysilane (TEOS), as examples, is deposited over the nitride frame
18
.
An anti-reflective coating (ARC)
22
comprising, for example, an organic polymer, may be deposited over the hard mask
20
, and a resist
24
typically comprising an organic polymer is deposited over the ARC
22
. ARC
22
is typically used to reduce reflection during exposure because reflection can deteriorate the quality of the image being patterned.
The resist
24
is exposed, patterned and etched to remove exposed portions, typically in a positive exposure process, although, alternatively, a negative exposure process may be used to pattern the resist
24
.
After an ARC
22
open step, the semiconductor wafer
10
is exposed to an etch process, e.g. an anisotropic etch e.g. in a plasma reactor, to transfer the resist
24
pattern to the hard mask
20
, the nitride frame
18
and nitride layer
14
, as shown in FIG.
2
. Reactive ion etching (RIE) is often used to transfer the pattern to the hard mask
20
, the nitride frame
18
and nitride layer
14
. The etch may stop on the polysilicon
16
and silicon
12
, or alternatively, the etch may include a slight over-etch of silicon
12
to ensure that no portions of the nitride layer
14
remain over the top surface of the silicon
12
. The active areas (AA) are protected by the hard mask
20
and therefore are not etched.
The resist
24
and the ARC
22
are removed, e.g., in a dry strip using oxygen plasma, as shown in FIG.
3
. Portions of the wafer
10
not covered by the hard mask
20
are etched to form shallow trenches within the wafer
10
using the hard mask
20
to pattern the trenches, opening the STI area
40
, as shown in FIG.
3
. The polysilicon
16
, collars
15
, and silicon
12
are etched off to a fixed depth, for example, 300 to 350 nanometers, which forms the shallow trench isolation at
40
.
The hard mask
20
is typically removed prior to any further processing steps. Usually, the trench
40
formed in the silicon
12
and polysilicon
16
is filled with an insulator such as an oxide, and the wafer
10
is then polished by a chemical-mechanical polish (CMP) process down to at least the pad nitride layer
14
surface, leaving oxide in the trenches
40
to provide isolation between devices (not shown). The top portion
42
of polysilicon
16
functions as the strap by providing an electrical connection between the deep trench
13
capacitor and the active area AA, which may comprise a transistor of a memory cell (not shown). The strap
42
is also referred to in the art as a buried strap. If there is no overlap (e.g. at
42
) of polysilicon
16
and silicon
12
, then no electrical connection is made between a memory cell capacitor and access transistor, resulting in a defective DRAM device
10
.
A problem with the prior art method and structure shown in
FIGS. 1-3
is that the strap
42
resistance can be high, which makes the storing and retrieving of information to and from the DRAM storage capacitor slow. If the strap
42
has a high resistance, a longer amount of time is required to charge up the storage capacitor. Also, a high strap
42
resistance requires a large amount of power, because the surrounding circuitry (not shown) must be used longer, thereby using more current and power.
What is needed in the art is an STI method resulting in a lower strap resistance for memory devices.
SUMMARY OF THE INVENTION
The present invention provides a method of shallow trench isolation for semiconductor devices.
In accordance with a preferred embodiment, a selective TEOS material is used to cap deep trenches prior to active area hard mask deposition, lithography and etch steps. A first insulator is selectively formed over deep trench polysilicon fill, with none of the first insulator material being formed over the pad nitride layer. The first insulator acts as a protective barrier for the strap region during subsequent processing steps, resulting in a strap region having a lower resistance.
Disclosed is a preferred embodiment for a STI method for a semiconductor wafer, comprising providing a wafer including a first semiconductor material, the first semiconductor material comprising element regions; depositing a pad nitride over the first semiconductor material; forming at least two trenches within the first semiconductor material and pad nitride, leaving a portion of first semiconductor material and pad nitride in a region between the two trenches; depositing a second semiconductor material over the trenches to fill the trenches to at least at height below the first semiconductor material top surface; selectively forming a first insulator over the second semiconductor material; and removing the pad nitride and a portion of the first semiconductor material between at least two trenches to isolate element regions of the wafer.
Also disclosed is a preferred embodiment for a method of manufacturing a memory device, the method comprising providing a semiconductor wafer comprising a first semiconductor material; depositing a pad nitride over the first semiconductor material; forming a plurality of memory cells on the semiconductor wafer, each memory cell including a deep trench proximate an element region, the deep trenches being filled with a second semiconductor material to a height below the top of the first semiconductor material; selectively forming a first insulator over t

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