Strained silicon forming method with reduction of threading...

Details Strained silicon forming method with reduction of threading... Strained silicon forming method with reduction of threading...

2006-09-05

2006-09-05

Menz, Douglas M. (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Heterojunction

C257S009000, C257S018000, C257S065000

Reexamination Certificate

active

07102153

ABSTRACT:
A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed SixGe1-x; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.

REFERENCES:
patent: 5614435 (1997-03-01), Petroff et al.
patent: 6541788 (2003-04-01), Petroff et al.
patent: 2005/0037556 (2005-02-01), Grutzmacher

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