Strained-silicon for CMOS device using amorphous silicon...

Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material

Reexamination Certificate

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C438S482000, C438S486000

Reexamination Certificate

active

07429749

ABSTRACT:
An integrated circuit (IC) includes a strained-silicon layer formed by deposition of amorphous silicon onto either a region of a semiconductor layer that has been implanted with ions to create a larger spacing between atoms in a crystalline lattice of the semiconductor layer or a silicon-ion layer that has been epitaxially grown on the semiconductor layer to have an increased spacing between atoms in the silicon-ion layer. Alternatively, the IC includes a strained-silicon layer formed by silicon epitaxial growth onto the region of the semiconductor layer that has been implanted with ions. The IC also preferably includes a CMOS device that preferably, but not necessarily, incorporates sub-0.1 micron technology. The implanted ions may preferably be heavy ions, such as germanium ions, antimony ions or others. Ion implantation may be done with a single implantation process, as well as with multiple implantation processes.

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patent: 6682980 (2004-01-01), Chidambaram et al.
patent: 6703293 (2004-03-01), Tweet et al.
patent: 2004/0232422 (2004-11-01), Forbes
Nobuyuki Sugii, Digh Hisamoto, Katsuyoshi Washio, Natsuki Yokoyama, and Shin′chiro Kimura, “Enhanced Performance of Strained-Si MOSFETs on CMP SiGe Virtual Substrate,” IEEE, 2001, 0-7803-7052-X/01, p. 1-4.
Paul Comita, AnnaLena Thilderkvist, and Arkadii V. Samoilov, “Applied Materials FEOL Seminar 2002,” Oct. 29, 2002, p. 1-37.
K. Rim, S. Koester, M. Hargrove, J. Chu, P. M. Mooney, J. Ott, T. Kanarsky, P. Ronsheim, M.Ieong, A. Grill, and H.-S. P. Wong, “Strained Si NMOSFETs for High Performance CMOS Technology,” IEEE 2001 Symposium on VLSI Technology Digest of Technical Papers, 2001, p. 59 (1-2).
Yee-Chia Yeo, Qiang Lu, Chenming Hu, Tsu-Jae King, T. Kawashima, M. Oishi, S. Mashiro, and J. Sakai, “Enhanced performance in sub-100 nm CMOSFETs using strained epitaxial silicon-germanium”, IEEE International Electron Device Meeting Technical Digest, pp. 753-756, San Francisco, CA, Dec. 2000, www.eecs.berkeley.edu/IPRO/Summary/01abstracts/ycyeo.1.html, p. 1-4.

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