Strained Fin FETs structure and method

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor

Reexamination Certificate

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Details

C257S194000, C257S349000, C438S157000, C438S283000, C438S285000, C438S286000

Reexamination Certificate

active

06849884

ABSTRACT:
A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.

REFERENCES:
patent: 6475869 (2002-11-01), Yu
patent: 20030151077 (2003-08-01), Mathew et al.
patent: 20040031979 (2004-02-01), Lochtefeld et al.
patent: 20040061178 (2004-04-01), Lin et al.
patent: 20040145019 (2004-07-01), Dakshina-Murthy et al.

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