Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2002-03-19
2003-10-21
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S194000, C257S349000
Reexamination Certificate
active
06635909
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the field of semiconductor manufacturing and, more specifically, to a method for forming double-gated field effect transistors.
2. Description of the Related Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever-increasing device densities is particularly strong in complementary metal oxide semiconductor (CMOS) technologies, such as the in the design and fabrication of field effect transistors (FETs). FETs are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.). Unfortunately, increased device density in CMOS FETs often results in degradation of performance and/or reliability.
One type of FET that has been proposed to facilitate increased device density is a double gated field effect transistor. Double gated FETs use two gates, one on each side of the body to facilitate scaling of CMOS dimensions while maintaining acceptable performance. In particular, the use of the double gate increases the gate area, which allows the transistor to have better current control without increasing the gate length of the device. As such, the double gated FET is able to have the current control of a larger transistor without requiring the device space of the larger transistor.
Unfortunately, several difficulties arise in the design and fabrication of double gated CMOS transistors. First, the relative dimensions of a double gated transistor are such that it is difficult to reliably fabricate one that has reliable performance and minimum feature size. Second, the threshold voltage of a double gated transistor is highly dependent upon the material used for the two gates. In particular, current fabrication techniques have generally resulted in a double gated transistor that has either too high a threshold voltage or too low a threshold voltage. For example, if the gates are doped the same polarity as the source, the threshold voltage will generally be near zero. Conversely, if the gates are doped the opposite polarity of the source, then the threshold voltage will be approximately one volt. Neither result is desirable in most CMOS applications.
Thus, there is a need for improved device structures and methods of fabrication of double gated CMOS devices that provide improved threshold voltage of the resulting double gated CMOS without overly increasing fabrication complexity.
Physical strain on the channel material in FET can improve carrier mobility. Strain induced on planar p-type metal oxide semiconductor field effect transistor (MOSFET) devices has been shown to increase hole mobility in excess of 30%. This invention provides these advantages to thin semiconductor bodies that are vertically arranged on a substrate; as such, the invention combines greater channel control with greater carrier mobility.
SUMMARY OF THE INVENTION
The asymmetric strained Fin Field effect transistor has an insulator and a semiconductor structure on the insulator. The structure includes a central portion and first and second ends extending from the central portion. A first gate is positioned on a first side of the central portion of the structure, a strain-producing layer between the first gate and the first side of the central portion of the structure, and a second gate on a second side of the central portion of the structure. The insulator is a buried oxide layer and the central portion of the structure is silicon. The strain-producing layer has a sufficient concentration of germanium to produce strain within the central portion to enhance carrier mobility without producing sufficient dislocations to reduce overall performance of the transistor. The first and second ends are source and drain regions, respectively. The concentration of germanium is between 10% and 40%. The different gates may be doped differently to adjust VT. The gates may also be doped similarly.
The symmetric strained Fin field effect transistor has an insulator and a semiconductor structure on the insulator. The structure is a Fin body having a central portion having silicon and silicon germanium and end portions comprising silicon. A first gate is positioned on a first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the structure. The first gate and the second gate may again be doped similarly or differently (as with the asymmetric strained situation).
The method of forming a transistor includes forming a silicon layer on an insulator, etching a first portion of the silicon layer to create a first opening, depositing a first gate in the first opening and etching a second portion of the silicon layer to create a second opening opposite the first opening. After the etching of the second portion, the silicon layer has a silicon structure on the insulator having a central portion and Fins extending from ends of the central portion. The invention forms a strain-producing layer upon a portion of the silicon structure facing the second opening which forms a second gate in the second opening, and removes the first gate and the second gate from all portions of the silicon structure except from the central portion.
The method of forming an asymmetric strained Fin field effect transistor includes forming a silicon layer on an insulator, etching a first portion of the silicon layer to create a first opening, depositing a first gate in the first opening, etching a second portion of the silicon layer to create a second opening opposite the first opening. After the etching of the second portion, the silicon layer has a silicon structure on the insulator having a central portion and Fins extending from ends of the central portion. The invention forms a silicon germanium layer upon a portion of the silicon structure facing the second opening, forms a second gate doped differently or similarly to the first gate in the second opening and removes the first gate and the second gate from all portions of the silicon structure except the central portion.
The method of forming strained Fin field effect transistors includes forming a silicon structure on an insulator, forming stress on one or both sides of the silicon structure, having a central portion and Fins extending from ends of the central portion, depositing a first gate and a second gate on sides of the silicon structure, and removing the first gate and the second gate from all portions of the silicon structure except the central portion.
Physical strain on the channel material in FETs can improve carrier mobility. Strain induced on planar p-type metal oxide semiconductor field effect transistor (MOSFET) devices has been shown to increase hole mobility in excess of 30%. This invention provides these advantages to thin semiconductor bodies that are vertically arranged on a substrate; and, as such, the invention combines greater channel control with greater carrier mobility.
REFERENCES:
patent: 6399970 (2002-06-01), Kubo et al.
patent: 6512252 (2003-01-01), Takagi et al.
patent: 0921575 (1999-06-01), None
Clark William F.
Fried David M.
Lanzerotti Louis D.
Nowak Edward J.
Chadurjian, Esq. Mark F.
International Business Machines - Corporation
McGinn & Gibb PLLC
Meier Stephen D.
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