Store processing method in a pipelined cache memory

Details Store processing method in a pipelined cache memory Store processing method in a pipelined cache memory

1994-03-16

1996-04-16

Elmore, Reba I.

Boots, shoes, and leggings

395415, 395472, 395473, 364DIG1, G06F 1206

Patent

active

055091377

ABSTRACT:
A cache memory apparatus and microprocessor therewith has a first address register for a tag memory and a second address register for a data memory, a tag entry decoder and a data entry decoder. Lower order bits of the contents stored in the first address register are transferred to the second address register through a transferring path in a write operation. Tag comparison and a data write of a result of the preceding comparison are executed in parallel in the same clock period, and thereby speed of processing is higher in the case of consecutive write operations at a write hit.

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patent: 5148536 (1992-09-01), Witek et al.
patent: 5163142 (1992-11-01), Mageau
"CMOS Design for Super LSI", p. 181, 5.29 Apr. 25, 1989.

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