Store-in-cache processor means for clearing main storage

Details Store-in-cache processor means for clearing main storage Store-in-cache processor means for clearing main storage

1980-10-06

1983-08-16

Thomas, James D.

Boots, shoes, and leggings

G06F 1300, G06F 906

Patent

active

043995063

ABSTRACT:
Inhibit means prevents a store-in-cache (SIC) from requesting or receiving any line fetch from MS when a clear line (CL) command is issued by a CPU to main storage (MS).
Two CPU modes are provided: (1) an initial storage validation mode and (2) an instruction processing mode. The system operator controls the first mode so that a CPU can execute the CL command during system initialization without any prior data fetch from MS. In the second mode, the CL command is executed as a component of a program instruction fetched from MS that can clear a block in main storage.
In a multiprocessor (MP), the CL command by any CPU requests a line store of pad data into an addressed line in MS only after each other SIC copy directory is searched and any found conflicting line is invalidated. Line castout to MS is prohibited for a conflicting line found in a cache by the CS command, which would have been a normal operation for other types of CPU commands. After any line conflict is found for any other cache in the MP, the completion of the CL command is delayed by cancelling the line pad write request to MS. Then the IE repeatedly reissues the CL command until all found conflicting lines are invalidated. As soon as no conflict is found in any copy directory, the currently issued CL command is completed by not cancelling the pad data request to MS, so that pad bytes are then written into the line in MS.

REFERENCES:
patent: 3723976 (1973-03-01), Alvarez et al.
patent: 3735360 (1973-05-01), Anderson et al.
patent: 3771137 (1973-11-01), Barner et al.
patent: 4056844 (1977-11-01), Izumi
patent: 4136386 (1979-01-01), Annunziata et al.
patent: 4152764 (1979-05-01), Connors et al.
patent: 4280176 (1981-07-01), Tan
patent: 4290103 (1981-09-01), Hattori
patent: 4293910 (1981-10-01), Flusche et al.
patent: 4314331 (1982-02-01), Porter et al.
patent: 4317168 (1982-02-01), Messina et al.
patent: 4332010 (1982-05-01), Messina et al.
patent: 4342084 (1982-07-01), Sager et al.
IBM System/370, Principles of Operation (Form Number GA22-7000), pp. 133-135.

Affiliated with

Also associated with

Rating

Store-in-cache processor means for clearing main storage does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Store-in-cache processor means for clearing main storage, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Store-in-cache processor means for clearing main storage will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-817805